CET4805 Lab 6

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New York University *

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4805

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Electrical Engineering

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Jan 9, 2024

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NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York FALL, 2021 Component and Subsystem Design II CET 4805 SECTION OL85 Meeting Day: Monday LAB 6: State machine design in VHDL & programming Submission Date 11/22/2021 Lab Objective: The objective of this lab is to follow a VHDL program to implement 1 4-bit stepper motor sequence with direction control. The input are clk and dir and the output is a 4-bit vector name

Q. The state_machine is defined with four values: S0, S1, S2, S3. The internal signal is declared as TYPE: state_machine and will be assigned values in the CASE assignment group. Lab Overview: 1.Creating a New Project 2. Open a new VHDL Device Design file (File > New) by highlighting VHDL File. Type the VHDL codes shown in Text Box. 3. Save the VHDL file as machine.vhd as part of our project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save. 4.Compile the machine.vhdl 5. Open a new vwf file (File > New) 9. Select node finder and insert all nodes created from machine.vhdl 10. Run the simulation for your program by clicking on Run Functional Simulation in the toolbar or by going to Simulation > Run Functional simulation.

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Vector waveform / Clock diagrams Vector waveform Simulation for output/after simulation Conclusion and summary: Throughout this lab, I successfully wrote a VHDL entity that implements logic functions that follow a VHDL program to implement 1 4-bit stepper motor sequence with direction control.