Lab 2-CEG2136-2 (1)

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Lab #2: Design, Simulation and Experimental Verification of Sequential Logic Circuits CEG2136 A03 - Computer Architecture I Fall 2023 Course Coordinator: Dr Voicu Groza Teaching assistant (TA): Bidisha Group 14 Jenny Farag - 300299753 Bwen Kayembe Entus - 300300868 Experiment date: September 28 2023 Submission date: October 10 2023 1
Theoretical Part: Introduction: The purpose of this lab is to build two sequential circuits in the Quartus II environment and to implement the circuits on the Altera DE2-115 board. When testing the circuits, one circuit must display the counter outputs as binary values on the Altera Board LEDs , and the other circuit must use the oscilloscope to record the waveforms of the JK flip flops. This lab allowed us to begin familiarizing ourselves with the oscilloscope. Objectives: The purpose of the lab was to familiarize ourselves as well as gain new knowledge on how to properly convert functional requirements into logic circuits and their implementation using the Altera DE2-115 board and/or the oscilloscope, which in our case, is what we used. This lab session also had its goal to enter the design of synchronous counters using Quartus II graphics editor, as well as, introduce us to the design of sequential circuits based on Altera’s Quartus development environment. Lots of learning was done, as its other main goal was to help us get more familiar with understanding the implementation of sequential circuits and how to test them out using FPGA. Problem: Based on the state diagrams, two different synchronous circuits are developed in this lab. For each circuit, a simulation and a live demonstration (two distinct methods) will be performed in order to confirm that the outcomes match the state diagrams. Designing sequential circuits based on the presented state diagrams is the problem for this lab. Figure 1: block diagram and state diagram of modulo 6 counter 2
Solution: To solve the problem, we created the sequential circuits, JK Flip Flops, NOTs, and ANDs were used. A clock and reset inputs, three JK flip flops, and three outputs were shown in part 1 diagram. A clock and reset inputs, four JK Flip Flops, and four outputs were shown in the diagram for part Design: 1. Presentation of design: Part 1: 3 bit synchronous modulo 6 counter: Present State Next state Synchronous inputs Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 J 2 K 2 J 1 K 1 J 0 K 0 000 010 0X 1X 0X 001 XXX XX XX XX 010 110 1X X0 0X 011 101 1X X1 X0 100 000 X1 0X 0X 101 100 X0 0X X1 110 011 X1 X0 1X 111 XXX XX XX XX Table 1: 3 bit synchronous modulo 6 counter Using the JK flip-flop truth table as a starting point, derive the K-maps and the equations that go with them based on the synchronous inputs. J2 Q1Q0 Q2 00 01 11 10 0 0 X 1 1 1 X X X X 3
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J2=Q1 Table 2: K-Map for J2 K2 Q1Q0 Q2 00 01 11 10 0 X X X X 1 1 0 X 1 K2=Q0’ Table 3: K-Map for K2 J1 Q1Q0 Q2 00 01 11 10 0 1 X X X 1 0 0 X X J1=Q2’ Table 4: K-Map for J1 K1 Q1Q0 Q2 00 01 11 10 0 X X 1 0 1 X X X 0 K1=Q0 Table 5: K-Map for K1 J0 Q1Q0 Q2 00 01 11 10 0 0 X X 0 1 0 X X 1 J0=Q1Q2 Table 6: K-Map for J0 K0 Q1Q0 4
Q2 00 01 11 10 0 X X 0 X 1 X 1 X X K0=Q1’ Table 7: K-Map for K0 Figure 2: Circuit diagram for modulo 6 counter Part 2: 4 bit synchronous BCD counter ABCD ABCD J A K A J B K B J C K C J D K D 0000 0001 0X 0X 0X 1X 0001 0010 0X 0X 1X X1 0010 0011 0X 0X X0 1X 0011 0100 0X 1X X1 X1 0100 0101 0X X0 0X 1X 5
0101 0110 0X X0 1X X1 0110 0111 0X X0 X0 1X 0111 1000 1X X1 X1 X1 1000 1001 X0 0X 0X 1X 1001 0000 X1 0X 0X X1 1010 XXXX XX XX XX XX 1011 XXXX XX XX XX XX 1100 XXXX XX XX XX XX 1101 XXXX XX XX XX XX 1110 XXXX XX XX XX XX 111 XXXX XX XX XX XX Table 8: 4-bit synchronous BCD counter Based on the K-maps for each JK flip-flop, here are the equations for each synchronous input. JA CD AB 00 01 11 10 00 0 0 0 0 01 0 0 1 0 11 X X X X 10 X X X X JA=BCD Table 9: K-Map for JA KA CD AB 00 01 11 10 00 X X X X 01 X X X X 6
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11 X X X X 10 0 1 X X KA=D Table 10: K-Map for KA JB CD AB 00 01 11 10 00 0 0 1 0 01 X X X X 11 X X X X 10 0 0 X X JB= CD Table 11: K-Map for JB KB CD AB 00 01 11 10 00 X X X X 01 0 0 1 0 11 X X X X 10 0 0 X X KB= CD Table 12: K-Map for KB JC CD AB 00 01 11 10 00 0 1 X X 01 0 1 X X 11 X X X X 7
10 0 0 X X JC= A’D Table 13: K-Map for JC KC CD AB 00 01 11 10 00 X X 1 0 01 X X 1 0 11 X X X X 10 X X X X KC= D Table 14: K-Map for KC JD CD AB 00 01 11 10 00 1 X X 1 01 1 X X 1 11 X X X X 10 1 X X 1 JD= 1 Table 15: K-Map for JD KD CD AB 00 01 11 10 00 X 1 1 X 01 1 X X 1 8
11 X X X X 10 1 X X 1 KD= 1 Table 16: K-Map for KD Figure 3: Logic diagram of a 4 bit synchronous BCD Figure 4: BCD Counter to 7-segment display decoder 9
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Figure 5: MOD60 to 7-segment display decoder Figure 6: MOD60 pin assignments for the 14 pins of the two 7-segments displays 2. Discussion of components used: During this lab multiple components were used, such as: Quartus II (web edition) Altera DE2-115 board with - USB-Blaster cable - Power supply 12V/2A 10
Oscilloscope Keysight/Agilent MSOX2012A ( 2 analog + 8 digital channels) Probe Coaxial cable Wires Ribbon cable First of all, the AND gate. A gate where the output is 1 if and only if both inputs have a value of 1. Otherwise it's 0. Secondly, NOT gate, is a gate where the output is 1 if the input is 0, and vice versa. Finally, a JK Flip Flop, is a gated SR Flip Flop that has a clock input that prevents the invalid output when both S and R are 1. Multiple components were used throughout this lab. Oscilloscope is an instrument used to display and analyze the waveform of electronic signals. There is also the Altera DE2-115 Board, which allows us to visualize and test our designed circuits from the Quartus software, consisting of a circuit board with multiple pins, buttons and LEDs. There is also the coaxial cable that conducts electrical signals. Using it as an output for the clock from the Altera DE2-115 board to the oscilloscope. The ribbon cable is a cable with many conducting wires. This was used to connect the Altera DE2-115 board to the oscilloscope. And there wires were used to connect the two ribbon cables together. 3. Solution: For both circuits, we used JK Flip Flop together with a Count and Clock input. Additionally, we employed NOT and AND gates. Each Flip Flop was connected in a way that was consistent with the equations we discovered while completing our K-maps. We uploaded the modulo 6 counter onto the Altera board after creating the circuit designs. We utilized the oscilloscope to simulate and see the operation of our circuit for a BCD counter. Figure 7 displays the results. Figure 7: Simulation of BCD on the oscilloscope 4. Challenging problems: Here are some of the challenges that were faced during the lab session: Properly assigning the pins Configuring the MOD60 and BCD counter using the 7-segment decoder 11
Connecting our decoders to the altera board (which is it was done through the oscilloscope Understanding the lab The instructions were pretty hard to understand as it was extremely wordy and was filled with a lot of technical term that were not quite familiar to either of our vocabulary Compiling all diagrams It took lots of tries as well as trials and errors. A big challenge that we faced during this lab was that we didn't have enough time. Perhaps, the trouble that we were facing was having to get the Altera Board to execute with our BCD. But we would always make sure to ask for help from our TA’s and brainstorming in order to generate solutions. Simulation and Verification Figure 8: Waveform for the BCD logic diagram This showcases how our logic diagram is functioning properly. As shown above, our reset is equally able to fulfill its purpose. Figure 9: Waveform for Modulo 6 counter 12
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Figure 9: Waveform for Mod60 Overall we were able to have a functional running diagram ( For the BCD ) it was easy to run its simulation and its result was shown on the oscilloscope. We were only able to witness the working diagram with the BCD diagram as it was a longer task to configure the MOD 60 diagram/counter. We were still able to draw it out and run its simulation as well as assign the right pins, but we were incapable of witnessing its function as we did not run it on the oscilloscope or on the Altera board. The theoretical and experimental results match up the experiment circuit design portion as the waveforms we obtained show the simulation results matching with the truth table from the design part. Discussion and conclusions: This lab included two components, and we utilized several tools to complete this lab. This lab was done in two parts, where one part was obtaining the 3-bit counter on the DE2-115 board. And the other part, was the output of the logic circuit displayed on the oscilloscope. When we attempted to set the board, we were having troubles doing so, it was displaying the right thing. However, the oscilloscope, the machine did end up working after multiple tries. 13
Appendix (pre lab) 14
15
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