HW Report Template (2)

docx

School

University of North Texas *

*We aren’t endorsed by this school

Course

4760

Subject

Electrical Engineering

Date

Apr 3, 2024

Type

docx

Pages

Uploaded by MateGuineaPig3377

Page 1 of 10 EENG XXXX HW X Report Template Name: Click or tap here to enter text. Due: MM/DD/YYYY

Page 2 of 10 Table of Contents Design ......................................................................................................................................................... 3 Block diagrams ........................................................................................................................................ 3 Overall design ...................................................................................................................................... 3 Subcomponents .................................................................................................................................... 4 Design explanation .................................................................................................................................. 5 Functionality ........................................................................................................................................ 5 Design Choices .................................................................................................................................... 5 Results ......................................................................................................................................................... 5 Generated Schematic ............................................................................................................................... 5 Waveforms .............................................................................................................................................. 6 Table/Calculations ................................................................................................................................... 7 Overall Design ..................................................................................................................................... 7 Subcomponent test cases ..................................................................................................................... 8 References ................................................................................................................................................... 9

Page 3 of 10 * Delete the text in between the * * symbols . This text is just to help explain. Note: figures should be labeled using figure captions, which you can add by right clicking an image and selecting the “Insert caption” option. Note: The table of contents should be updated once you finish the report. Click inside the table of contents and then click the “Update table” button that appears. * Design Block diagrams Overall design Figure 1-Example top module: 8:1 mux with overall ports, subcomponents and intermediate signals shown *Include a block diagram besides the generated RTL schematic that shows with clear labels all of the ports, intermediate signals and any subcomponents (if using structural design) for your top level module. If using structural design, the dataflow between components should be clearly visible. The diagram can be drawn by hand (or digitally using apps like OneNote, Microsoft Word, etc) or made using graphic design editors (ex: draw.io (free), Photoshop, Krita (free), LaTex (package: Tikz, free)). You should do this part of the report before starting to code so you can have a blueprint/reference to follow when coding. Make sure to use the same names in your diagram as you do in your code. * Overall component: *8x1 multiplexer* Parameters: d_w – data width (for inputs and outputs) Input ports: Port name Bit width Purpose I0, I1, I2, I3, I4, d_w = 4 Data inputs

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

Page 4 of 10 I5, I6, I7 Sel 3 Selection line, selects data input to send to output Output ports: Port name Bit width Purpose Y d_w = 4 Data output Necessary intermediate signals: *If there are no intermediate signals, you can remove this section name and table* Port name Bit width Purpose Z1, Z2 d_w = 4 Outputs of 4x1 muxes, inputs to 2x1 mux Subcomponents *If there are no subcomponents and this is a completely behavioral design, you can delete this subsection.* Figure 2 - Example subcomponent (2x1 mux) Subcomponent: 2x1 mux Input ports: Port name Bit width Purpose I0, I1 d_w = 4 Data inputs Sel 1 Select line, selects which of the 2 data inputs to send to data output Output ports:

Page 5 of 10 Port name Bit width Purpose Y d_w = 4 Data output *Necessary intermediate signals: * *If there are no intermediate signals, you can remove this section name and table* Port name Bit width Purpose Subcomponent: 2x1 mux Input ports: Port name Bit width Purpose I0, I1, I2, I3 d_w = 4 Data inputs Sel 2 Select line, selects which of the 4 data inputs to send to data output Output ports: Port name Bit width Purpose Z d_w = 4 Data output *Necessary intermediate signals: * *If there are no intermediate signals, you can remove this section name and table* Port name Bit width Purpose Design explanation Functionality

Page 6 of 10 *Explain the functionality of the top level design you are implementing and any significant components such as CUs. If you are implementing a structural design, explain the dataflow from the top level inputs, through the subcomponents and to the final output(s). Example structural design functionality explanation: To form the top level 8x1 mux, there are first 2 instances of 4x1 muxes that split the 8 data inputs between them and share the 2 LSB of the top level select lines. The outputs of the 4x1 muxes are then sent to a 2x1 mux that uses the MSB of the top level select lines and whose output is mapped to the top level output.* *You should represent selective behavior in a table similar to this: * Select input Resulting output 00 I0 01 I1 10 I2 11 I3 *In addition to the table, please include a brief sentence explaining what the table shows. Example: As seen by the table, the select input determines which of the 4 data inputs is sent to the output.s Make sure that the design is clearly explained and do not depend on your code to be able to be self- explanatory (i.e. someone should be able to understand your design from your report without you having to be there to explain it). * Design Choices *Explain any extra design choices you make here (especially anything/any choices not specified in the assignment instructions). If the output data width is not specified, please explain your choice of output data width and how you handle the output. * Results Generated Schematics

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

Page 7 of 10 Figure 3 - 8x1 mux block design ** Include the block diagram of the top module and any significant subcomponents such as CUs. Briefly state that the ports of the generated block diagram match the ports of the block diagram drawing you made yourself in the design section. ** Figure 4 - 8x1 mux RTL schematic **Include the generated RTL schematic of the top module. If the design is large and a single screenshot doesn’t clearly show the schematic, then split the screenshot in as many parts as necessary. If the design is behavioral, you do not need to explain the generated RTL schematic. If the design is structural, you need to verbally explain how the dataflow in the generated RTL schematic matches that of your block diagram. Ex: In the generated schematic, there are 2 4:1 muxes receiving the (split) 8 overall data inputs and using the 2 LSB of the overall select lines. The outputs of the 4x1 muxes are fed as inputs to a 2x1 mux with the MSB of the overall select lines. The output of the 2x1 mux is the overall output. This structure and dataflow matches that of our design. ** Waveforms

Page 8 of 10 Figure 5 – Overall Waveforms *Take a screen snip (Windows: Window key + Shift + S) or crop a screenshot (Window key + PrtScn) of only the relevant parts of the waveforms for the top module and any significant subcomponents that require testing, like CUs ( you don’t need to show parts of the Vivado software ). You need to visibly show all of the relevant inputs and outputs (and potentially even intermediate signals) for all of the test cases . Show the waveforms for all the calculations for the test cases you include, not just the final output(s). You can show all the required test cases in a single screenshot or split them into multiple screenshots for each test case. If there are too many waveforms to fit into one screenshot, you can split the waveforms in multiple screenshots. If you do split the waveforms, please put a figure label before each test case saying which test case the screenshots are for. Please make sure that the labels and values of the waveforms (i.e. the numbers and the column on the left saying the value at the cursor) are visible for each test case. Including dividers would be helpful. If your values are multiple bits wide, don’t expand vertically to show the bits individually, at most you should just change the radix to binary. If you use a radix besides binary in the waveforms, please also use that radix in your calculations.* Table/Calculations Overall Design Test Case # (*0ns to 5ns*): CU# SourceA SourceB A B Oper Calculated Op Simulated Op Match CU1 A B 0011 0010 MULT 0110 0110 Yes CU2 C D 0101 0100 ADD 1001 1001 Yes CU3 CU1 CU2 0110 1001 LT 1111 1111 Yes … Test Case # (*5ns to 10ns*): CU# SourceA SourceB A B Oper Calculated Op Simulated Op Match CU1 A B 0011 0010 MULT 0110 0110 Yes CU2 C D 0101 0100 ADD 1001 1001 Yes CU3 CU1 CU2 0110 1001 LT 1111 1111 Yes

Page 9 of 10 … *Edit these tables to include all the relevant inputs, outputs and intermediate signals of your test cases and put the values for the outputs you calculated vs what was actually obtained in the waveforms. Then give a brief explanation such as the example below about whether the results you obtained from the waveforms/simulations is correct. * *Example explanation: As can be seen by the table, the waveform output values for both test cases match the calculated values. This means the design works properly. * *If there is a difference between the calculations and the waveforms, at least attempt to write an explanation here as to the probable reason why there is a difference.* Subcomponent test cases Test Case # (*0ns to 5ns*): A B Oper Calculated Op Simulated Op Match 0011 0010 MULT (000) 0110 0110 Yes 0101 0100 ADD (001) 1001 1001 Yes 0110 1001 LT (010) 1111 1111 Yes … Test Case # (*5ns to 10ns*): A B Oper Calculated Op Simulated Op Match 0011 0010 MULT (000) 0110 0110 Yes 0101 0100 ADD (001) 1001 1001 Yes 0110 1001 LT (010) 1111 1111 Yes … *If any test cases were provided for subcomponents, you need to also include tables of their calculations vs what was actually obtained in the waveforms. You only need to do this for the subcomponents that were provided test cases in the assignment, not all subcomponents. If there weren’t any test cases provided for subcomponents, you can delete this subsection.* References

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

Page 10 of 10 **If you use any figures (including ones you write on top of) or outside references, please cite them here. Otherwise you can remove this section. **