Lab 05 Unsigned 2-bit integer

pdf

School

University of Cincinnati, Main Campus *

*We aren’t endorsed by this school

Course

2060C

Subject

Electrical Engineering

Date

Apr 3, 2024

Type

pdf

Pages

7

Uploaded by reed0000

Report
Lab 05: Unsigned 2-bit Adders Reed Doneghy, doneghrm, M14914110 Aaron Linneman, linnemac, M14557088 02/27/24 Project 1 001 Tuesday 12:30
Requirement Specifications: In this lab, we were to design a two-bit unsigned adder that only deals with positive numbers. The first number has two bits X 1 (Y 1 ) and X 0 (Y 0 ) where X 1 (Y 1 ) is the most significant bit. The unsigned 2-bit full adder has 5 inputs and 3 outputs where each S i is a sum bit, C 2 is the carry-out of the last stage. This will add x and y.
Final Circuit Diagram: Here is the full adder. We combined two of these to make the full 2-bit adder. We used the carry from the first adder as the initial carry of the next adder. Here is the final circuit design
Your preview ends here
Eager to read complete document? Join bartleby learn and gain access to the full version
  • Access to all documents
  • Unlimited textbook solutions
  • 24/7 expert homework help
Circuit Photo: Here is the picture of our circuit
TA Signature: Total Test Patterns:
Here are out test patterns for the circuit Common Questions
Your preview ends here
Eager to read complete document? Join bartleby learn and gain access to the full version
  • Access to all documents
  • Unlimited textbook solutions
  • 24/7 expert homework help
What is the utilization of your components (i.e., total number of used gates divided by the number of IC components? Can you think of any way(s) you could improve the component utilization? a. The total number of components used is 3 and the number of gates used is 10 which gives us a utilization rate of 3.3333. We used almost all of the gates on the XOR and AND chips How many test vectors were required to assure correctness of the circuit? a. We used 10 test vectors to ensure correctness and they were all correct with testing What is the longest circuit delay in terms of “gate delays”? a. The longest gate delay is 3 gates. That is from either the carry from the first full adder to the carry of the second adder Define in detail the contribution of each team member to the accomplishment of the project for each phase (i.e., Pre-lab, In-Lab, and Post-Lab). The idea is that over the semester all team members share equally in all aspects of the laboratory activity (requirements, design, simulation, test, implementation, and report writing). a. Aaron helped make the test patterns and helped Reed while he built the circuit. Aaron added pictures and made entries under the pictures. Reed did the common questions and submitted the lab. Total Time: 1 hour and 50 minutes