1007ICT_Module 4 Workshop Assessment

I need the solution to chapter 10, #19 this is from Matlab a practical introduction to programming and problem solving

You want to design a grading machine. The input is 3-bit score (0-7). The output is a 7-seg controller that shows the grade. You want to display A. when the score is 7 B. when the score is 5,6 C. when the score is 3,4, D. when the score is 1,2 F. when the score is 0

Number 15

Q1: A sequential circuit has one inputs X and one output (Z) is used to detect the sequence 1011. The output Z=1 when the circuit detect the sequence 1011, otherwise Z=0. Sketch the stated diagrams of the following specifications: 1. Mealy model and the overlap is allowed. 2. Mealy model and the overlap is not allowed. I need to solve the question step by step and in clear handwriting.

Please help me to do this

mechatronics home work

A Moving to the next question prevents changes to this answer. Question 2 To convert (11110101)2 to BCD code, how many steps you use? What are they? What is the result of conversion? (write your answer in the box below (do not include this in your pdf file)

Don't use ai to answer I will report you answer

Q1: A sequential circuit has one inputs X and one output (Z) is used to detect the sequence 1011. The output Z=1 when the circuit detect the sequence 1011, otherwise Z =0. Sketch the stated diagrams of the following specifications: 1. Moor model and the overlap is allowed. 2. Moor model and the overlap is not allowed. 3. Mealy model and the overlap is allowed. 4. Mealy model and the overlap is not allowed. 5. Discuss your results.

I need the right choice from the expert.

The logic function implemented by the multiplexer circuit is (ground implies a logic "0") 4x1 MUX 1。 1₁ 1₂ 13 S₁ S₂ P Q Y -F

The subject is: Automatic Control Systems  Please send the answer by typing ONLY. I don't want any handwritten. Also, don't copy-paste from the net, as plagiarism will be counted.

Design a code converter that converts a decimal digit from BCD to excess-3 code, the input variables are organized as (A B C D) respectively with A is the MSB, the output variables are organized as (W XY Z) respectively with W is the MSB, put the invalid decimal numbers as don't care. W=A+BD+BC' W=A+BD+BC, W=A'+BD+BC W= BC'D'+B'D+B'C

A CPU is equipped with a cache; accessing a word takes 45 clock cycles if the data is not in cache memory and 5 clock cycles if the data is in the cache. What is the effective memory access time in clock cycles if the hit ratio is 85%? O 10 clock cycles O 9 clock cycles O 11 clock cycles O 12 clock cycles