Lab 8 Report

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Electrical Engineering

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Feb 20, 2024

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ECEN 248 - Lab Report Lab Number: 8 Lab Title: Counters, Clock Dividers, and Debounce Circuits Section Number: 507 Student’s Name: Om Dalvi Student’s UIN: 831004188 Date: 3/30/23 TA: Hesam Mazaheri

Objectives: The purpose of this lab is to reinforce our knowledge of sequential circuits by introducing the binary counter, which is an important synchronous sequential circuit. We will use the counter to tackle two use cases: I/O debouncing and frequency division. Through this, we will learn more about using Verilog HDL, implementing our designs on the Zybo Z7-10, and synchronous circuits. Design: Experiment Part 1: 1. Create a new Vivado project called lab8. 2. Create a file called “clock_divider.v”, and use the code from the manual to create a module describing a clock frequency divider. 3. Using “clock_divider.xdc” from the course files, synthesize and implement the design on the Zybo Z7-10 4. Connect the Zybo to the logic analyzer and configure it so that only the relevant channels are showing. Turn on the Zybo board and program it, then press Run and Auto Scale on the logic analyzer. 5. Use the cursor tool to measure the wavelengths of each clock signal output by the circuit. Experiment Part 2: 1. Create a file called “half_adder.v” and describe a half adder circuit using dataflow Verilog. 2. Create a file called “up_counter.v” and use the code from the manual to create a module describing a 3-bit up-counter. 3. Simulate the up-counter and observe the waveform to ensure it is functioning properly. 4. Once the u-counter is properly functioning, create a file called “top_level.v and use the code snippet from the manual to create a module that connects all the synchronous components we created so far together. 5. Create a file called “top_level.xdc” and use the code snippet from the manual to write an XDC file that will allow us to program the Zybo with our “top_level.v” code. 6. Synthesize and Implement the design, then program the Zybo board and test that all functions are working as intended. Experiment Part 3: 1. Add “Bounce_tb.v”, “withDebounce.v” and “noDebounce.v” to project from the course files. 2. Test “Bounce_tb.v” with both “withDebounce.v” and “noDebounce.v” and observe the differences between them. 3. Take a closer look at the code for “withDebounce.v” and gain understanding of how the debouncing circuit works

Results: Through this lab, most data was collected in the form of screenshots, which can all be found in Appendix A. Besides the screenshot, The frequency and periods of the input and output clocks from “clock_divider.v” are all collected below. ClkIn Period (ns) ClkIn Frequency (MHz) clkOut Bit clkOut Period (ns) clkOut Frequency (MHz) 8 125 3 64 15.6250 4 128 7.8125 5 256 3.9063 6 512 1.9531 Conclusion: After completing this lab, I feel as though I have a stronger understanding of how synchronous circuits are used as well as why they are beneficial compared to circuits without a clock. I also gained experience in using a logic analyzer to examine the results of a circuit using hardware, which was very similar to using the waveforms generated by testbench cases in Vivado. Post-lab Deliverables: Answers to Lab Questions: 1. Experiment Part 1, 4.a The original ClkIn signal is a clock with a 8ns period (125MHz frequency), while the 4 ClkOut signals have periods of 64ns, 128ns, 256ns, and 512ns (15.625MHz, 7.8125MHz. 3.9063MHz, 1.9531MHz, respectively). Each clock signal is connected to the 3 rd , 4 th . 5 th . And 6 th clock signals respectively as well. This proves the formulas F out = F ¿ n and T out = n ∗ T ¿ to be true, as all values observed follow both formulas. 2. Experiment Part 2, 2.b The clock signal (Image 6) has a rising edge once every 20 ns. Using the formula F = 1 T , we can plug in T = 20 ns to get F = 1 20 ns = 1 20 ∗ 10 − 9 hz = 50 MHz . 3. Experiment Part 2, 2.c The testbench (Image 6) holds the counter in reset for the first 40ns of the test. 4. Experiment Part 2, 2.d

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The testbench (Image 6) holds the enable LOW for the first 80ns of the test, 40ns longer than the reset is held for. 5. Experiment Part 2, 2.f The counter (Image 6) rolls over after Count reaches seven(111), the highest number possible with the three available bits. Whenever Count equals seven, the Carry2 signal is HIGH, so we can use that to tell when the counter is about to roll over. 6. Experiment Part 2, 3.a Using the formula F out = F ¿ 2 n , and plugging in the values F ¿ = 125 MHz and n = 26 , we get F out = 125 MHz 2 26 = 125 ∗ 10 6 Hz 67,108,864 = 1.8626 Hz . 7. Experiment Part 3, 1.b The circuit in noDebounce.v does not work as expected, which we know by analyzing its waveform (Image 9). As we can see, the “bouncing” causes the button to input two separate presses when the button was only pressed once, which in turn causes the LEDs to display the incorrect count. 8. Experiment Part 3, 2.a The circuit in withDebounce.v works as expected, which is determined by analyzing its waveforms (Image 10). We can see that regardless of the button bouncing”, the input is synchronized and only gives one rising edge per button press. 9. Experiment Part 3, 2.c In the circuit described in withDebounce.v, a couple things happen to help debounce the signal. The first always block acts as the synchronizer, taking the BTN input and returning a synchronized output called “ Synchronized ” on each rising edge of the clock signal. The second always block is used as the counter, increasing Count by one on each rising edge of the clock signal. The rest of the section concerning the debounce circuit contains assign statements used to connect all the loose wires up, such as giving notMSB the inverse value of the most significant bit, outputting the most significant bit’s value as the Debounced signal, connecting the reset of the counter to the inverse of the Synchronized signal, and setting the En of the counter to the AND product of notMSB and Synchronized . 10.

Appendix A: Screenshots Image 1. Source code for clock_divider.v Image 2. Waveform generated by a Zybo Z7-10 running clock_divider.v

Image 3. Wavelengths measured using cursors Image 4. Source code for half_adder.v

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