Lab6_Report

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Texas A&M University, –Central Texas *

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Electrical Engineering

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Feb 20, 2024

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ECEN 248 - Lab Report Lab Number: 6 Lab Title: Introduction to Behavioral Verilog and Logic Synthesis Section Number: 508 Student’s Name: Om Dalvi Student’s UIN: 831004188 Date: 3/10/23 TA: Hesam Mazaheri

Objectives: This lab is designed to teach students about behavioral Verilog and how we can use the HDL code that we write to program the FGA on a Zybo Z7-10 board in order to test components described in Verilog. Design: To begin this lab, we started by describing familiar components (1bit 2:1 MUX, 4bit 2:1 MUX, and 4bit 4:1 MUX) using behavioral Verilog in order to get a feel for it. We wrote out code for each of these components and tested them using the testbench files provided. Next, we moved on to developing a 4:2 Encoder, 2:4 Decoder, and Priority 4:2 Encoder using behavioral Verilog. For each of these components, we repeated the same process of developing code and testing it using the provided testbench files. An additional step we took with thee files was to connect a Zybo Z7-10 board to our computer and generating a bitstream file which was used to instruct the FPGA contained on the board. We were then able to use the board to physically test out our circuits. Results: As results for this lab. I collected a series of screenshots showing the code I developed as well as the waveforms and console output generated by the included testbench files. These can all be found in the Post-lab Deliverables section of the report. Conclusion: After completing this lab, I now have a much better understanding of how code created using an HDL can be implemented using logic synthesis techniques in Verilog, as well as how to use behavioral Verilog. Post-lab Deliverables: 1. Include the source code with comments for all modules you simulated. You do not have to include test bench code. Code without comments will not be accepted! 2. Include screenshots of all waveforms captured during simulation in addition to the test bench console output for each test bench simulation.

Image 1. Waveform and console log for two_one_mux.v Image 2. Source Code for two_one_mux.v Image 3. Waveform and console log for four_bit_mux.v Image 4. Source Code for four_bit_mux.v

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Image 5. Waveform and console log for mux_4bit_4to1.v Image 6. Source code for mux_4bit_4to1.v Image 7. Waveform and console log for two_four_decoder.v Image 8. Source code for two_four_decoder.v

Image 9. Waveform and console log for four_two_encoder.v Image 10. Source code for four_two_encoder.v Image 11. Waveform and console log for priority_encoder.v Image 12. Source code for priority_encoder.v 3. Provide a comparison between behavioral Verilog used in this week’s lab and the structural and dataflow Verilog used in last week’s lab. What might be the advantages and disadvantages of each?

The behavioral Verilog used in this week's lab is much more like a coding language, versus the structural and dataflow Verilog used in last week's lab which was more gate oriented. The behavioral Verilog feels much more efficient and powerful to use, while structural and dataflow Verilog allows you to fully understand the circuit being built. 4. Compare the process of using a breadboard to implementing a digital circuit on an FPGA. State some advantages and disadvantages of each. Which process do you prefer? Using a breadboard is a much more manual task than implementing digital circuits on FPGA, as they require you to place all your gates, supply them with power, and wire them all up yourself. In my opinion using FPGAs with HDLs is much more efficient as it allows you to more rapidly test out new ideas, especially for more complex designs.

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Related Questions

3. Discussion: 1. Convert the gray code 01011001 to decimal number and show your work. 2. Convert the gray code 00101101 to binary number and show your work. 3. Design a 8-bit binary to gray code conversion circuit using logic gates and verify your design. 4. Design a 8-bit gray to binary code conversion circuit using logic gates and verify your design.
parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.
a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)

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