Lab 3 Report

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Texas A&M University, –Central Texas *

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248

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Electrical Engineering

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Feb 20, 2024

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ECEN 248 - Lab Report Lab Number: 3 Lab Title: Rudimentary Adder Circuits Section Number: 507 Student’s Name: Om Dalvi Student’s UIN: 831004188 Date: 2/16/23 TA: Hesam Mazaheri
Objectives: The purpose of this lab is to design a half adder, full adder, and ripple carry adder as well as build them using logic gates. This is to introduce us to simple addition using circuits as well as to reinforce our understanding of how to use truth tables and Karnaugh maps to create Boolean equations and design a circuit. Design: The first step in the process of this lab is to create truth tables for our half adder and full adder circuits. We can then use these to create Karnaugh maps, which we can then in turn use to derive Boolean equations for each output. We can then use these equations as blueprints for creating our schematics. All of these can be found in the Post-lab Deliverables section. With all the preparation completed, now all we have to do is build the circuits. I began by first connecting one each of the 74ALS08(AND), 74ALD32(OR), and 74ALS86(XOR) ICs across partition lines on the breadboard and connecting group and power to their lower left and upper right legs respectively. This will give me access to enough gates to test all circuits without needing to do any more later. Once those are in place I can follow my schematics to wire up each circuit and test all the outputs. Results: During the lab, I successfully created the circuits as outlined in my schematics. All outputs matched the truth tables I designed, which tells me that the circuits worked as intended. Photographs of these circuits are included below. Half Adder Circuit Full Adder Circuit Carry Ripple Adder Circuit
Conclusion: Overall, this lab has given me some insight to how simple arithmetic is done in circuits, as well as a better understanding of how to use truth tables and K-maps to create schematics and circuits. Post-lab Deliverables: 1. Provide all design items found in the pre-lab deliverables. If you found that a design needed corrections while executing the lab, supply the updated version of that material. Figure 1. Half adder truth table Figure 2. Full adder truth table
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Figure 3.Full/half adder K-Maps & Equations
Figure 4.Schematics for all three adder circuits 2. Determine the worst-case propagation delay for your full adder design. Assume each gate has the same delay of 1 unit. Show the maximum delay path in your schematic. The maximum delay path is known as the critical path for that particular combinational block. The maximum delay path for my full adder circuit consisted of three gates, so the worst-case propagation delay would be 3 units.
Figure 5. Maximum delay path for full adder circuit 3. Design a 2-bit carry ripple adder assuming you only have half adder circuits and OR gates to work with. Draw up a schematic for your design using half adder building blocks and OR gates. Be sure the clearly label all inputs and outputs of your blocks.
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