Homework2_Solutions

pdf

School

Purdue University *

*We aren’t endorsed by this school

Course

270

Subject

Electrical Engineering

Date

Feb 20, 2024

Type

pdf

Pages

Uploaded by SuperHumanQuailMaster1039

ECE 270 Homework 2 Solutions Spring 2024 1. Consider the following CMOS circuit and the resistance table. If Vdd=1.1V and Vin=0V, what is the Vout, total current flow and the total power? Note: round to the nearest tenth for each answer ON Resistance OFF Resistance N-Channel 100 Ω 1 M Ω P-Channel 200 Ω 1 M Ω a. Vout = 1.1 V, I = 1.1 µA, P = 1.21 µW b. Vout = 1.1 V, I = 0.56 µA, P = 0.616 µW c. Vout = 0.0 V, I = 5.7 µA, P = 28.5 µW d. Vout = 0.0 V, I = 6.6 µA, P = 33.0 µW e. None of the others Answer: a Reasoning: - Vin = 0V, PMOS => on, NMOS => off, creates a voltage divider circuit - 200 ohms across PMOS, 1M ohms across NMOS, meaning almost all voltage left across NMOS => Vout = Vdd which is 1.1V - Current through circuit can be found using ohms law, 1.1V/1M ohm => 1.1µA - Power = IV, 1.1µA * 1.1V => 1.21µW

ECE 270 2 Spring 2024 2. Which of the following Boolean expressions represents the below circuit: a. OUT = (D + A . (B + C)) b. OUT = (D + A . (B + C))’ c. OUT = (D.(A + B.C)) d. OUT = (D.(A + B.C))’ e. None of the others Answer: b Reasoning: - Parallel gates => OR, Series gates => AND - D in parallel with A, B, C => D + (A,B,C) - A in series with (B,C) => D + A.(B,C) - B and C in parallel => D + A.(B + C), when this boolean expression is true the output is zero not one, therefore take the complement of the expression => (D + A.(B + C))’ - Notice the top half of the circuit is just the complement of the bottom half 3. What is the fall time of an output signal in digital electronics? a. Time required for an input pulse to rise from 10% to 90% of its maximum value b. Time required for an output pulse to fall from 90% to 10% of its maximum value c. Time required for an input pulse to fall from 90% to 10% of its maximum value d. Time required for an output pulse to rise from 10% to 90% of its maximum value e. None of these Answer: b Reasoning: - Fall time is the amount of time it takes for a signal to go from 90% of its maximum value to 10% of its maximum value - The opposite applies for the rise time of a signal

ECE 270 3 Spring 2024 4. As per the above timing diagram, what is the rise propagation delay (tpLH) of the gate? a. tpLH = 6ns b. tpLH = 5ns c. tpLH = 4ns d. tpLH = 3ns e. None of the others Answer: c Reasoning: - tpLH represented as the time it takes for the output signal to go high - Delay time begins being measured at the 50% mark of the input signal that causes the output to go high

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

ECE 270 4 Spring 2024 - Delay time ends at the 50% mark of the output signal going from high to low, the difference between the two times is the tpLH 5. A CMOS Circuit operating at 100 MHz, with a load capacitance of 1 nF (nanofarads) dissipates 1600 mW of power. If the operating frequency of the circuit increases by 50%, and the supply voltage gets halved, what is the new power dissipated (consider same load capacitance)? a. 1200 mW b. 800 mW c. 600 mW d. Data insufficient to calculate the new power e. None of the others Answer: c Reasoning: 6. Which of the following circuits correctly represents the function Y = (P(Q+R))’

ECE 270 5 Spring 2024 a. b. c. d. d. None of the others Answer : d Reasoning:

ECE 270 6 Spring 2024 Q NMOS and R NMOS should in parallel , and in series with P NMOS 7. Which of the following truth tables correspond to the CMOS circuit shown below ? a.

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

ECE 270 7 Spring 2024 b. c. d. e. None of the others Answer:b Reasoning: Y = 0 when (A*B) + C = 0

ECE 270 8 Spring 2024 8. Which of the following is correct ? a) M.(M’+N) = M.N b) M+(N.O) = (M+N)(M+O’) c) (M+N)’ = M’.N d) M.(N.O) = (M.N’).O e) None of the above Answer: a Reasoning: M.M’+M.N = M.N (M.M’ = 0) 9. With Vdd = 3 V, what is the lower boundary for logic high? What is the upper boundary for logic low? Note: do not round and use the 30%/70% rule of thumb a. Lower boundary for logic high = 2.1 V, Upper boundary for logic low = 0.9 V b. Lower boundary for logic high = 2.7 V, Upper boundary for logic low = 0.7 V c. Lower boundary for logic high = 1.5 V, Upper boundary for logic low = 1.5 V d. Lower boundary for logic high = 2.0 V, Upper boundary for logic low = 1.0 V e. None of the others Answer: a Using the 30%/70% rule, the lower boundary is 70% of VDD and the higher boundary is 30% of VDD. Therefore, lower boundary is 2.1 V (0.7 * 3 = 2.1) and higher boundary is 0.9 V (0.3 * 3 = 0.9V) 10. Given the DC characteristics of two Logic families A and B, calculate the Low Noise margin (NML) for B -> A (output of B connected to input of A).

ECE 270 9 Spring 2024 a. 0.7 V b. 1.1 V c. 1.6 V d. 1.7 V e. None of the others Answer:b Reasoning: We are measuring the Low Noise Margin, and the output of B is connected to input of A. So, we should look at V_OL for B (as V_OL is output low) and V_IL (input low) for A and find the difference. 1.30V - 0.20V = 1.1V 11. Let a boolean function F = (a + c + e).(a + b’).(a’ + b’ + c’ + d’). The complement of the function F is a. ace + ab’ + a’b’c’d’ b. a’c’e’ + a’b + abcd c. (a’+ c’+e’).(a’+ b).(a + b + c+ d) d. (a + c+ e).(a + b’).(a’+ b’ + c’+ d’) e. None of the others Answer: b Reasoning: F’ = ((a + c + e).(a + b’).(a’ + b’ + c’ + d’))’ (using De Morgan’s) F’ = (a+c+e)’ + (a+b’)’ + (a’ + b’+ c’+ d’) F’ = (a’c’e’) + (a’b) + (abcd) 12. The simplified form of the boolean expression AB + A(B +C) + B(B +C) is a. B + AC

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

ECE 270 10 Spring 2024 b. AC +AB c. A +BC d. C + AB e. None of the others Answer: a 13. A given boolean expression F = XYZ + X’ZWY + XYZ’ + W’YZ + X’ZW’ + X’ZWY’ + WYZ. The simplified form of this expression is a.XYZ + X’Z + YZ b. XZ + YZ c. XY + X’Z d.W’Y + YZ e.None of the others Answer: c 14. Consider a function F = (A'+C'+D) . (A+C') . (D'+B) . (A'C'+AD). Which of the following is the most simplified expression of F' ? Hint: Use DeMorgan's law to write out the inversion first and then use other properties to simplify it as much as possible. a. DB' + A'D' b. AC'

ECE 270 11 Spring 2024 c. ACD' + A'C + DB' + AD' + CD' d. A'C + AD' + DB' e. None of the others Answer: d 15. A half adder (HA) below adds the two input bits X, Y to generate two output bits Carry, Sum. The functionality of HA is described in the truth table below. Change the verilog codes to dataflow statements based.

ECE 270 12 Spring 2024 Which of the following Verilog modules correctly represents half adder circuit? a. module half_adder (input X, input Y, output Carry, output Sum); assign Sum = X ^ Y; assign Carry = X & Y; endmodule b. module half_adder (input X, input Y, output Carry, output Sum); assign Sum = X ^ Y; assign Carry = a ^ b; endmodule c. module half_adder (input X, input Y, output Carry, output Sum); assign Sum = X & Y; assign Carry = X & Y; endmodule d. module half_adder (input X, input Y, output Carry, output Sum); assign Sum = X + Y; assign Carry = X | Y; endmodule e. None of the others Answer: a Carry is the output of an XOR operation between X and Y. Sum is the output of an AND operation between X and Y. This can be realized from the truth table. 16. Which of the following expressions represent the dual of the boolean expression: z + z’(v’w + xy)

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

ECE 270 13 Spring 2024 a. z’ + z(vw’ + x’y’) b. z.(z’ + ((v’ + w).(x + y))) c. z’.(z + ((v + w’).(x’ + y’))) d. z’.(z’(v’w + xy)) e. None of the others Answer: b 17. Which logic diagram realizes 2-input OR gate using 2-input NAND gate a

ECE 270 14 Spring 2024 b. c. d. e. None of the others Answer: D

ECE 270 15 Spring 2024 18. A given boolean expression is F = W’ . (WXYZ)’. The simplified form of this expression is a. W b. WXYZ c. W’ d. W + X + Y + Z e. None of the others Answer: c Reasoning: - (WXYZ)’ = W’ + X’ + Y’ + Z’ by DeMorgan’s Law - W’ . (W’ + X’ + Y’ + Z’) = W’.W’ + W’.X’ + W’.Y’ + W’.Z’ - W’.W’ + W’.X’ + W’.Y’ + W’.Z’ = W’ + W’.X’ + W’.Y’ + W’.Z’ - A + A.B = A bc simplifies to A.(1 + B) = A.1 = A - Similar process to simplify the above expression into W’ 19. A given boolean expression is F = A + (AB’CD). The simplified form of this expression is a. 1 b. 0 c. A d. A’ e. None of the others Answer: c Reasoning: - F = A.(1 + B’CD) by distributive property - F = A.1 by 1 + anything = 1 - F = A

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

ECE 270 16 Spring 2024 20. Parity bit is the simplest form of error detecting code. An odd-parity scheme is when the added parity bit makes the total number of 1s in the bitstream to an odd number. For example, Let's assume the input bitstream is 0011. This data has an even number of 1s (2). Under the odd-parity scheme, the parity bit for this bitstream is 1, as adding the parity bit (0011 1 )will make the total number of 1s to be an odd number (3). An odd-parity generator circuit generates the parity bit based on the input data. The truth table for an odd-parity generator for a 3-bit stream of data is shown below A B C Parit y 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 Which of the following options represent the boolean function that generates the parity bit based on the 3-inputs A,B,C (in the simplified form) a. Parity = A ⊕ B ⊕ C b. Parity = AB + BC + AC c. Parity = A ⊕ B d. Parity = (A ⊕ B ⊕ C)’ e. None of the others Answer: d Reasoning: - First, notice that A = 0, B = 0, and C = 0 produces a Parity = 1 - This immediately eliminates b and c as options - Also notice that if parity is dependent on if there is an even or odd number of 1s, it shouldn’t matter where the 1s are assigned - This eliminates a bc since the parenthesis mean the arrangement of the inputs matter

ECE 270 17 Spring 2024 - This leaves d as the remaining possible answer - (0 ⊕ 0 ⊕ 0)’ = 0’ = 1 - (1 ⊕ 0 ⊕ 0)’ = (1 ⊕ 0)’ = 1’ = 0 (same for all inputs with only one 1) - (1 ⊕ 1 ⊕ 0)’ = (0 ⊕ 0)’ = 0’ = 1 (same for all inputs with two 1s) - (1 ⊕ 1 ⊕ 1)’ = (0 ⊕ 1)’ = 1’ = 0 - Thus the correct answer is d