CH 4&5 T_F Key
.docx
keyboard_arrow_up
School
California State University, Fullerton *
*We aren’t endorsed by this school
Course
409
Subject
Electrical Engineering
Date
Jun 21, 2024
Type
docx
Pages
10
Uploaded by MagistrateJellyfish20290
1.
Media access controls refer to the need to control when computers transmit.
a.
True
b.
False
2.
The data link layer accepts messages from the network layer and controls the hardware that transmits them.
a.
True
b.
False
3.
Only the sender of a data transmission needs to be concerned about the rules or protocols that govern how it communicates with the receiver.
a.
True
b.
False
4.
Most computer networks managed by a host mainframe computer tend to use a form of media access control called contention.
a.
True
b.
False
5.
Polling is the process of permitting all clients to transmit or receive at any time.
a.
True
b.
False
6.
With roll-call polling, a server polls clients in a consecutive, pre-arranged priority list.
a.
True
b.
False
7.
Token passing is a term that refers to hub polling, in which one computer starts a poll and passes it to the next computer on a multipoint circuit.
a.
True
b.
False
8.
With contention, a computer does not have to wait before it can transmit. A computer can transmit at any time.
a.
True
b.
False
9.
Contention is widely used with Ethernet local area networks.
a.
True
b.
False
10. Controlled access MAC approaches work well in a large network with high usage.
a.
True
b.
False
11. There are three commonly used controlled access techniques: access requests, access demands, and polling.
a.
True
b.
False
12. The two categories of network errors are lost data and delimited data.
a.
True
b.
False
13. If a computer transmits a message containing “ABC” and the destination computer receives “abc” as the message, the message is corrupted.
a.
True
b.
False
14. Data transmission errors typically are distributed uniformly in time.
a.
True
b.
False
15. Undesirable stray electrical voltage can cause data communication errors.
a.
True
b.
False
16. Gaussian noise is a special type of attenuation.
a.
True
b.
False
17. The thermal agitation of electrons causes impulse noise.
a.
True
b.
False
18. Crosstalk occurs when the signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel.
a.
True
b.
False
19. Attenuation refers to the loss of signal strength.
a.
True
b.
False
20. When the signals from two circuits combine to form a new signal that falls into a frequency band reserved for another signal, this is called intermodulation noise.
a.
True
b.
False
21. The physical and data link layers of wired Ethernet have been refined over the years as a collection of standards under the IEEE 802.3 workgroup.
a.
True
b.
False
22. The distance between repeaters or amplifiers on a telephone circuit is determined by the amount of power gained per unit length of the transmission.
a.
True
b.
False
23. When we amplify the signal on an analog circuit, we also amplify any noise that is present on the circuit.
a.
True
b.
False
24. For effective error detection and correction, extra error detection “data” must be included with each message
a.
True
b.
False
25. In an odd parity-checking scheme, the parity bit is set to make the total number of ones in the byte (including the parity bit) an even number.
a.
True
b.
False
26. Parity checking can only detect an error when an even number of bits are switched.
a.
True
b.
False
27. Cyclical redundancy check is one of the most popular polynomial error-checking schemes.
a.
True
b.
False
28. The simplest method for error correction is retransmission.
a.
True
b.
False
29. Another term for continuous ARQ is sliding window.
a.
True
b.
False
30. One type of forward error correction is the Hamming code.
a.
True
b.
False
31. Forward error correction is commonly used in satellite transmission.
a.
True
b.
False
32. HDLC is very similar to the SDLC synchronous data link protocol.
a.
True
b.
False
33. Overhead bits are used for error checking and marking the start and end of characters and packets.
a.
True
b.
False
34. Transmission efficiency refers to the percentage of bits transmitted without errors.
a.
True
b.
False
35. The data link layer accepts streams of bits from the application layer.
a.
True
b.
False
36. The data link layer is responsible for encoding the bit-stream as a series of electronic voltages.
a.
True
b.
False
37. The data link layer performs error detection.
a.
True
b.
False
38. The data link layer performs routing functions.
a.
True
b.
False
39. The data link layer organizes data from the physical layer and passes these coherent messages directly to the application layer.
a.
True
b.
False
40. Media access control is not very important in point-to-point with full duplex configuration.
a.
True
b.
False
41. Media access control is not very important in local area networks.
a.
True
b.
False
42. Media access control is not very important in a point-to-point with a half-duplex configuration.
a.
True
b.
False
43. Media access control is not very important in a multipoint configuration.
a.
True
b.
False
44. Media access control does not control when computers transmit.
a.
True
b.
False
45. Roll call polling cannot be modified to increase priority of clients or terminals.
a.
True
b.
False
46. Roll call polling does not require a server, host, or special device that performs the polling.
a.
True
b.
False
47. Roll call polling is also called token passing.
a.
True
b.
False
48. Roll call polling is a type of contention approach to media access control.
a.
True
b.
False
49. Roll call polling typically involves some waiting because the server has to wait for a response from the polled client or terminal.
a.
True
b.
False
50. In general, controlled approaches work better than contention approaches for small networks that have low usage.
a.
True
b.
False
51. In general, controlled approaches work better than contention approaches for large networks that have high usage.
a.
True
b.
False
52. In general, controlled approaches work better than contention approaches for all sizes of networks.
a.
True
b.
False
53. In general, controlled approaches do not require a host, server, or active monitor to assign media access control.
a.
True
b.
False
54. In general, controlled approaches have many collisions.
a.
True
b.
False
55. Using parity, the probability for detecting an error, given that one has occurred, is about 50% for either even or odd parity.
a.
True
b.
False
56. Using parity, the probability for detecting an error, given that one has occurred, is about 25% for either even or odd parity.
a.
True
b.
False
57. Using parity, the probability for detecting an error, given that one has occurred, is about 70% for even parity and 30% for odd parity.
a.
True
b.
False
58. Using parity, the probability for detecting an error, given that one has occurred, is about 30% for even parity and 70% for odd parity.
a.
True
b.
False
59. Using parity, the probability for detecting an error, given that one has occurred, is about 20% for either even or odd parity.
a.
True
b.
False
60. Using parity, the probability for detecting an error, given that one has occurred, is about 100% for either even or odd parity.
a.
True
b.
False
61. Synchronous transmission cannot be used on multipoint circuits.
a.
True
b.
False
Your preview ends here
Eager to read complete document? Join bartleby learn and gain access to the full version
- Access to all documents
- Unlimited textbook solutions
- 24/7 expert homework help
Related Questions
This is a single question. Can yo send the solution.
arrow_forward
What is a transmission gate? Draw its circuit circuit diagram. How does it operate? What is the need for a transmission gate? What is it disadvantage?
arrow_forward
The following data are transmitted in a serial communication system (P is the parity
bit). What parity is being used in each case?
a. ABCDEFGHP = 010000101
b. ABCDEFGHP = 011000101
c. ABCDP = 01101
d. ABCDEP = 101011
e. ABCDEP = 111011
arrow_forward
4. FIGURE 1 shows how a 3 to 8 line decoder (TTL 74138) can be used in conjunction with NAND gate (TTL
74133) to connect a set of switches to the data bus of a microprocessor system via buffers (TTL 74367).
Answer the following questions relating to the diagram:
a) What address, in HEX, is required on the address bus in order toread the switches?
b) RD and MEMRQare control lines from the CPU. What must their
logic state be in order to read the switches?
Data bus
74 367
74 133
74 138
A15
D7
DO
EN
EN
Address
bus
RD
MEMRO
A4
A3
A1
AO
EN
TRUTH TABLE
C BA|O 1 2 3 4 5 6 7
0 0 00 1111
0 0 11 0 1 1 1 1 1 1
0 1 01 10 1 1 1 1 1
0 1 11 1 10 1 1 1 1
1 0 01 1i10 1 1 i
10 11 1 1 1 10 1 1
1 1 01 1 1 1 1 1 0 1
1 1 11 1 1 1 1 1 1 0
11
74 367
(part of)
FIGURE 1
Data enable
Data outputs
Input switches
arrow_forward
4. FIGURE 1 shows how a 3 to 8 line decoder (TTL 74138) can be used in conjunction with NAND gate (TTL
74133) to connect a set of switches to the data bus of a microprocessor system via buffers (TTL 74367).
Answer the following questions relating to the diagram:
a) What address, in HEX, is required on the address bus in order toread the switches?
b) RD and MEMRQare control lines from the CPU. What must their
logic state be in order to read the switches?
Data bus
74 367
74 133
74 138
A15
D7
DO
EN
EN
Address
bus
MEMRQ
A4
AO
EN
TRUTH TABLE
CBA 0 1 2 3 4 5 6 7
0 0 00 1 1 1 1 1 11
0 0 11 01 1 1 1 1 1
0 1 01 10 1 1 1 1 1
0 1 11 1 10 1 1 1 1
10 01 1 1 1 0 1 1 1
10 11 1 1 1 1 0 1 1
1 101 1 1 1 1 1 0 1
1 11 1 1 1 1 1 1 0
74 367
(part of)
1
arrow_forward
. The following is configured on a router
Router(config)# interface g0/0.10
Router(config-subif)# encapsulation dot1Q 20
Router(config-subif)# ip address 192.168.30.1 255.255.255.0
A packet is sent from the router out the subinterface to a trunk port on a switch. The switch will treat the packet as if it is on what VLAN?
. The following is configured on a router
Router(config)# interface g0/0.10
Router(config-subif)# encapsulation dot1Q 20
Router(config-subif)# ip address 192.168.30.1 255.255.255.0
A packet is sent from the router out the subinterface to a trunk port on a switch. The switch will treat the packet as if it is on what VLAN?
VLAN 20
VLAN 30
VLAN 10
The native VLAN
arrow_forward
1- Which layers are network support layers?
a. Physical Layer b. session Layer
2-What are the responsibilities of Data Link Layer?
a. Framing b. Encryption c. Mail services
3- What are the types of errors?
a. Compression b. Redundancy c. Single-Bit
4- What are the responsibilities of Application Layer?
c. Application Layers
Flow Control b. Translation c. Mail services
5- application layer protocols?
a. TFTP b. ICMP c. (ARP)
arrow_forward
b) Explain the main functions of i) the source and ii) the channel
coding blocks in a modern communication system. Error
correction is needed to ensure reliable transmission of signals,
but what is its disadvantage?
arrow_forward
Q14: Multiple Choice - The function of ARP is to what?
a. Translate from well known TCP ports to IP addresses.
b. Translate between IP addresses and TCP Ports
c. Translate from IP addresses to MAC addresses.
d. Translate from MAC addresses to IP addresses.
e. Address Routing Protocol - converts routes.
f. None of the above.
arrow_forward
Please assist with question 4
arrow_forward
3. What technology does the digital communication have in order to preserve more fidelity than analog
signal?
A. Cryptography
B. Encryption
C. Decryption
D. None of the above
arrow_forward
Please calculate the addresses of Bottom of Stack (BOS), Top of Stack (TOS), End of Stack (EOS). How many words of data are currently being stored in the stack?
arrow_forward
1) Compare between the Serial and Parallel ports from the following points of view
1- The length of the cable
3- Speed of transmission
2) For the AT89C51 programmer:
2- The maximum output swing
4- Number of internal registers
What is the total number of pins?, How many ports are there? How many bits does each port have?
3) What is the number of input pins and output pins for the game port?
4) In the address decoder circuit, what are exactly the address lines that should be used as the
inputs of the decoder that generates CS signals for twenty input/output devices, each of them
contain 5 internal registers?
5) There are
the parallel port.
inverted bits in the status register and inverted bits in the control register of
-
arrow_forward
Question 3
For the network 129.120.0.0/16. How many 129.120.0.0/24 subnets exist?
(numeric response)
1. How many bits are in the subnet portion?
(numeric response)
2. Subnet number range is from:
to:
(only provide the third subnet octate)
3. How may bits are in the host portion?
(numeric response)
4. Host address range is from:
to:
(only provide the fourth host octate)
5. Network number for first subnet is
(provide full ip address with mask)
6. Broadcast address for fırst subnet is
7. Netmask for 129.120.0.0/24 is:
arrow_forward
Design an 8-to-1-line multiplexer using a 3-to-8 line decoder and external gates.
arrow_forward
Write an 8085 assembly language program for the interfacing of 8255., where Port A and Port B are holding values, take those numbers from Port A and Port B, add them, and send the result at Port C. Note: Port A address is 00, Port B address is 01, Port C address is 02 and Control Register address is 03.
arrow_forward
4. A data signal with bipolar voltage levels is shown below. The decision
threshold is 0 volts. The logic levels are +1 volt for logic 1 and -1 volt for logic 0.
Noise with the P.D.F. shown corrupts the signal. Find the probability of error at
some instant of time on the condition that logic 0 is sent.
LOGIC 1
+1 VOLT
-2
1/2
دمت
~IN
kla
THRESHOLD
+2
NOISE P.D.F.
-I VOLT.
LOGIC 0
arrow_forward
Could you give brief explanation about LAN and WAN and write examples of network protocols that works on LAN and WAN?
Your answer cannot exceed 500 words.
arrow_forward
Given that the base address is FoH.
1. Create a new asm project “Lab2_Q1.asm". Assume that port A of 8255A PPI is
connected to 8085. Write assembly code to send the value of FFH to FoH. Enter a delay
of 2 ms for each transmission.
arrow_forward
EEE
arrow_forward
27.Transmission protocol serial asynchronous 8 bits ASCII, 1 parity bit, 9600 bps.
How long will it take for a kilobyte file to be transmitted through the link?
arrow_forward
(c) Write a VHDL code to implement the above counter using conditional statement "case". You
need not necessarily use a synchronous load mechanism.
arrow_forward
i need the answer quickly
arrow_forward
SEE MORE QUESTIONS
Recommended textbooks for you
Introductory Circuit Analysis (13th Edition)
Electrical Engineering
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:PEARSON
Delmar's Standard Textbook Of Electricity
Electrical Engineering
ISBN:9781337900348
Author:Stephen L. Herman
Publisher:Cengage Learning
Programmable Logic Controllers
Electrical Engineering
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education
Fundamentals of Electric Circuits
Electrical Engineering
ISBN:9780078028229
Author:Charles K Alexander, Matthew Sadiku
Publisher:McGraw-Hill Education
Electric Circuits. (11th Edition)
Electrical Engineering
ISBN:9780134746968
Author:James W. Nilsson, Susan Riedel
Publisher:PEARSON
Engineering Electromagnetics
Electrical Engineering
ISBN:9780078028151
Author:Hayt, William H. (william Hart), Jr, BUCK, John A.
Publisher:Mcgraw-hill Education,
Related Questions
- This is a single question. Can yo send the solution.arrow_forwardWhat is a transmission gate? Draw its circuit circuit diagram. How does it operate? What is the need for a transmission gate? What is it disadvantage?arrow_forwardThe following data are transmitted in a serial communication system (P is the parity bit). What parity is being used in each case? a. ABCDEFGHP = 010000101 b. ABCDEFGHP = 011000101 c. ABCDP = 01101 d. ABCDEP = 101011 e. ABCDEP = 111011arrow_forward
- 4. FIGURE 1 shows how a 3 to 8 line decoder (TTL 74138) can be used in conjunction with NAND gate (TTL 74133) to connect a set of switches to the data bus of a microprocessor system via buffers (TTL 74367). Answer the following questions relating to the diagram: a) What address, in HEX, is required on the address bus in order toread the switches? b) RD and MEMRQare control lines from the CPU. What must their logic state be in order to read the switches? Data bus 74 367 74 133 74 138 A15 D7 DO EN EN Address bus RD MEMRO A4 A3 A1 AO EN TRUTH TABLE C BA|O 1 2 3 4 5 6 7 0 0 00 1111 0 0 11 0 1 1 1 1 1 1 0 1 01 10 1 1 1 1 1 0 1 11 1 10 1 1 1 1 1 0 01 1i10 1 1 i 10 11 1 1 1 10 1 1 1 1 01 1 1 1 1 1 0 1 1 1 11 1 1 1 1 1 1 0 11 74 367 (part of) FIGURE 1 Data enable Data outputs Input switchesarrow_forward4. FIGURE 1 shows how a 3 to 8 line decoder (TTL 74138) can be used in conjunction with NAND gate (TTL 74133) to connect a set of switches to the data bus of a microprocessor system via buffers (TTL 74367). Answer the following questions relating to the diagram: a) What address, in HEX, is required on the address bus in order toread the switches? b) RD and MEMRQare control lines from the CPU. What must their logic state be in order to read the switches? Data bus 74 367 74 133 74 138 A15 D7 DO EN EN Address bus MEMRQ A4 AO EN TRUTH TABLE CBA 0 1 2 3 4 5 6 7 0 0 00 1 1 1 1 1 11 0 0 11 01 1 1 1 1 1 0 1 01 10 1 1 1 1 1 0 1 11 1 10 1 1 1 1 10 01 1 1 1 0 1 1 1 10 11 1 1 1 1 0 1 1 1 101 1 1 1 1 1 0 1 1 11 1 1 1 1 1 1 0 74 367 (part of) 1arrow_forward. The following is configured on a router Router(config)# interface g0/0.10 Router(config-subif)# encapsulation dot1Q 20 Router(config-subif)# ip address 192.168.30.1 255.255.255.0 A packet is sent from the router out the subinterface to a trunk port on a switch. The switch will treat the packet as if it is on what VLAN? . The following is configured on a router Router(config)# interface g0/0.10 Router(config-subif)# encapsulation dot1Q 20 Router(config-subif)# ip address 192.168.30.1 255.255.255.0 A packet is sent from the router out the subinterface to a trunk port on a switch. The switch will treat the packet as if it is on what VLAN? VLAN 20 VLAN 30 VLAN 10 The native VLANarrow_forward
- 1- Which layers are network support layers? a. Physical Layer b. session Layer 2-What are the responsibilities of Data Link Layer? a. Framing b. Encryption c. Mail services 3- What are the types of errors? a. Compression b. Redundancy c. Single-Bit 4- What are the responsibilities of Application Layer? c. Application Layers Flow Control b. Translation c. Mail services 5- application layer protocols? a. TFTP b. ICMP c. (ARP)arrow_forwardb) Explain the main functions of i) the source and ii) the channel coding blocks in a modern communication system. Error correction is needed to ensure reliable transmission of signals, but what is its disadvantage?arrow_forwardQ14: Multiple Choice - The function of ARP is to what? a. Translate from well known TCP ports to IP addresses. b. Translate between IP addresses and TCP Ports c. Translate from IP addresses to MAC addresses. d. Translate from MAC addresses to IP addresses. e. Address Routing Protocol - converts routes. f. None of the above.arrow_forward
- Please assist with question 4arrow_forward3. What technology does the digital communication have in order to preserve more fidelity than analog signal? A. Cryptography B. Encryption C. Decryption D. None of the abovearrow_forwardPlease calculate the addresses of Bottom of Stack (BOS), Top of Stack (TOS), End of Stack (EOS). How many words of data are currently being stored in the stack?arrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
- Introductory Circuit Analysis (13th Edition)Electrical EngineeringISBN:9780133923605Author:Robert L. BoylestadPublisher:PEARSONDelmar's Standard Textbook Of ElectricityElectrical EngineeringISBN:9781337900348Author:Stephen L. HermanPublisher:Cengage LearningProgrammable Logic ControllersElectrical EngineeringISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
- Fundamentals of Electric CircuitsElectrical EngineeringISBN:9780078028229Author:Charles K Alexander, Matthew SadikuPublisher:McGraw-Hill EducationElectric Circuits. (11th Edition)Electrical EngineeringISBN:9780134746968Author:James W. Nilsson, Susan RiedelPublisher:PEARSONEngineering ElectromagneticsElectrical EngineeringISBN:9780078028151Author:Hayt, William H. (william Hart), Jr, BUCK, John A.Publisher:Mcgraw-hill Education,
Introductory Circuit Analysis (13th Edition)
Electrical Engineering
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:PEARSON
Delmar's Standard Textbook Of Electricity
Electrical Engineering
ISBN:9781337900348
Author:Stephen L. Herman
Publisher:Cengage Learning
Programmable Logic Controllers
Electrical Engineering
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education
Fundamentals of Electric Circuits
Electrical Engineering
ISBN:9780078028229
Author:Charles K Alexander, Matthew Sadiku
Publisher:McGraw-Hill Education
Electric Circuits. (11th Edition)
Electrical Engineering
ISBN:9780134746968
Author:James W. Nilsson, Susan Riedel
Publisher:PEARSON
Engineering Electromagnetics
Electrical Engineering
ISBN:9780078028151
Author:Hayt, William H. (william Hart), Jr, BUCK, John A.
Publisher:Mcgraw-hill Education,