Practice_Final_Answers

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ECE2277 Practice Final ECE2277A: Practice Final Exam (Answers) Professor: Arash Reyhani & John McLeod Based on Exam given 2020 12 13 Part I: Number Systems [12 marks] 1. Convert (10110100) 2 into unsigned decimal and hexadecimal. [2 marks] Decimal 180 Hexadecimal B4 2. Convert (1110110) 2 into the appropriate decimal number according to the signed-magnitude, signed-1’s complement, and signed-2’s complement number systems. [3 marks] Signed-Magnitude 10 Signed-1’s Complement -137 Signed-2’s Complement -138 3. Convert decimal (35) 10 into 2421 binary code. [2 marks] 2421 code 00111011 4. What is the maximum range of signed-2’s complement and unsigned decimal numbers that can be accom- modated in a 9 -bit binary number system? (Please include negative signs as appropriate.) [4 marks] System Minimum Value Maximum Value Signed-Decimal -256 255 Unsigned-Decimal 0 511 5. What is the minimum number of bits needed to encode (26) 10 distinct quantities? [1 marks] Number of bits 5 1

ECE2277 Practice Final Part II: Logic Operations [4 marks] 6. Which logic operation with inputs x and y is represented by the Boolean function f ( x, y ) = ∑ (1 , 2 , 3) ? [1 mark] (a) AND (b) OR (c) NAND (d) NOR (e) XOR (f) XNOR b 7. Which logic operation with inputs x and y is represented by the Boolean function f ( x, y ) = Q (1 , 2 , 3) ? [1 mark] (a) AND (b) OR (c) NAND (d) NOR (e) XOR (f) XNOR d 8. What is the canonical sum-of-minterms (SOM) representation the logic operation x NAND y ? Please enter your answer as comma-separated indices (i.e. 0 , 1 , 2 , 3 ). [1 mark] f ( x, y ) = X (0 , 1 , 2) 9. What is the canonical product-of-maxterms (POM) representation the logic operation x XOR y ? Please enter your answer as comma-separated indices (i.e. 0 , 1 , 2 , 3 ). [1 mark] f ( x, y ) = Y (0 , 3) 2

ECE2277 Practice Final Part III: Boolean Expressions [20 marks] 10. What Boolean expression is represented by this Karnaugh map? [4 marks] yz wx 00 01 11 10 00 01 11 10 0 x x x 1 1 x 0 1 1 1 1 0 0 0 1 (a) f ( w, x, y, z ) = wx ′ + wyz + w ′ xy ′ (b) f ( w, x, y, z ) = wxz ′ + w ′ y + wxy ′ + w ′ x ′ (c) f ( w, x, y, z ) = wx ′ + wz + w ′ xy ′ (d) f ( w, x, y, z ) = wx ′ + wyz + w ′ y ′ z a 11. Which of the following Boolean expressions is equivalent to: f ( x, y, z ) = x ′ z + xz ′ + yz ′ [4 marks] (a) f ( x, y, z ) = ( x + y + z ) ( x ′ + z ′ ) (b) f ( x, y, z ) = ( x + y + z ) ( x ′ + y ′ + z ′ ) (c) f ( x, y, z ) = ( x + y ) ( x ′ + z ′ ) (d) f ( x, y, z ) = ( x + z ′ ) ( x ′ + z ) ( y ′ + z ) a 12. What are the minterms of: f ( x, y, z ) = x ′ y ′ + xy + yz ′ [4 marks] (a) f ( x, y, z ) = ∑ (1 , 2 , 6 , 7) (b) f ( x, y, z ) = ∑ (3 , 4 , 5) (c) f ( x, y, z ) = ∑ (0 , 1 , 2 , 5 , 6 , 7) (d) f ( x, y, z ) = ∑ (0 , 1 , 2 , 6 , 7) d 3

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ECE2277 Practice Final 13. Find the sum-of-products (SOP) simplification of: f ( w, x, y, z ) = X (0 , 1 , 2 , 5 , 8 , 10 , 11 , 13 , 15) , with don’t cares d ( w, x, y, z ) = X (3 , 4 , 7 , 14) . You may assume that all variables ( w, x, y, z ) and their complements ( w ′ , x ′ , y ′ , z ′ ) are available. [4 marks] yz wx 00 01 11 10 00 01 11 10 f ( w, x, y, z ) = wy + xz + w ′ z + x ′ z ′ 14. Find the product-of-sums (POS) simplification of: f ( w, x, y, z ) = X (0 , 2 , 4 , 7 , 8 , 9 , 10 , 11 , 14) , with don’t cares d ( w, x, y, z ) = X (1 , 5 , 6 , 12) . You may assume that all variables ( w, x, y, z ) and their complements ( w ′ , x ′ , y ′ , z ′ ) are available. [4 marks] yz wx 00 01 11 10 00 01 11 10 f ( w, x, y, z ) = ( w + x + z ′ ) ( w ′ + x ′ + z ′ ) 4

ECE2277 Practice Final Part IV: Combinational Circuits [18 marks] 15. The circuit diagram is shown below. The 3 -to- 8 decoder chip output is active high. You may assume it is always enabled. 2 2 x 2 1 y 2 0 z 3-to-8 Decoder 7 6 5 4 3 2 1 0 f ( x, y, z ) What function is implemented by this circuit? [2 marks] (a) f ( x, y, z ) = yz + x ′ y (b) f ( x, y, z ) = z ′ + y ′ (c) f ( x, y, z ) = y ′ (d) f ( x, y, z ) = xz ′ + y ′ d 16. Implement the Boolean expression: f ( x, y, z ) = x ′ z + yz ′ + y ′ z, using the following 4 × 1 multiplexer circuit. Set the data inputs D 0 , D 1 , D 2 , and D 3 to the appropriate input from z , z ′ , 1 , or 0 . You may assume the multiplexer is always enabled. [4 marks] f ( x, y, z ) 2 1 x 2 0 y 4 × 1 MUX D 3 D 2 D 1 D 0 Input Function D 0 = z D 1 = 1 D 2 = z D 3 = z ′ 5

ECE2277 Practice Final 17. Consider active high data lines D 0 and D 1 used as the inputs for a 2-to-1 priority encoder (where D 1 has the highest priority and D 0 has the lowest priority) as shown below. V V 2 0 x 2-to-1 Encoder 0 D 0 1 D 1 Obtain the Boolean expressions for the active low validity output V and the encoded output x in terms of D 0 and D 1 . [4 marks] V ( D 0 , D 1 ) = D ′ 1 D ′ 0 x ( D 0 , D 1 ) = D 1 18. Consider the combinational circuit shown below. Trace the circuit and express f 1 ( x, y, z ) and f 2 ( x, y, z ) as a standard form sum of products (SOP). [8 marks] x y x ′ z y z ′ f 2 ( x, y, z ) f 1 ( x, y, z ) f 1 ( x, y, z ) = y ′ + z f 2 ( x, y, z ) = x ′ y ′ z ′ + xz 6

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ECE2277 Practice Final Part V: Latches and Flip-Flops [14 marks] 19. The characteristic equation for a T flip-flop is Q ( t + 1) = Q ′ T + QT ′ . True or False . [1 mark] True . 20. The following flip-flop is triggered by the rising edge of the clock. Q T Q True or False . [1 mark] True . 21. You have developed a new and exciting type of flip-flop, the VW flip-flop! It has the following output: clear to 0 when V = 1 , W = 1 , set to 1 when V = 1 , W = 0 , no change when V = 0 , W = 1 , and complement when V = 0 , W = 0 . What is the characteristic equation of the VW flip-flop? [4 marks] V W Next State Q ( t + 1) 0 0 0 1 1 0 1 1 Q ( t + 1) = Q ′ w ′ + Qv ′ w + vw ′ 7

ECE2277 Practice Final 22. Consider the sequential circuit below. Q D Q CLK x y For this sequential circuit and the given timing diagram, which is the appropriate waveform for the output y ? The flip-flop was initialized to zero at the start. [4 marks] t CLK x (a) (b) (c) (d) b 8

ECE2277 Practice Final 23. Consider the sequential circuit below. Q T Q CLK x y For this sequential circuit and the given timing diagram, which is the appropriate waveform for the output y ? The flip-flop was initialized to zero at the start. [4 marks] t CLK x (a) (b) (c) (d) d 9

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ECE2277 Practice Final Part VI: Counters, Registers, and Finite State Machines [32 marks] 24. Consider a 4-bit synchronous binary up counter with a parallel load and an asynchronous clear. What combinational circuit is needed at the CLRN input to count the sequence from (0) 10 to (10) 10 , and repeat? LOAD 0 CLRN CLK I 3 0 I 2 I 1 I 0 A 3 A 2 A 1 A 0 COUNT 1 4-Bit Up Counter All control inputs are active high, and each value in the sequence should output for one clock cycle. Your answer should be a standard-form Boolean expression in terms of the count output A 3 A 2 A 1 A 0 . [2 marks] CLRN = A 3 A 1 A 0 25. Derive the state table for a synchronous counter that counts in the sequence (6 , 3 , 7 , 0 , 1) then repeats. As- sume this counter uses three flip-flops A , B , C ; where A represents the MSb in the output and C is the LSb in the output. Represent unused states as don’t care values (leave that row blank or write x s in the state table). [4 marks] A B C A ( t + 1) B ( t + 1) C ( t + 1) 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 x x x 0 1 1 1 1 1 1 0 0 x x x 1 0 1 x x x 1 1 0 0 1 1 1 1 1 0 0 0 10

ECE2277 Practice Final 26. Continue to develop the above counter that counts in the sequence (6 , 3 , 7 , 0 , 1) . How should the flip-flops be initialized at the start? The flip-flops have asynchronous active-low clear CLRN and preset PRN . The state is cleared to 0 when CLRN =0, PRN =1; set to 1 when CLRN =1, PRN =0; and normal flip-flop operation occurs when CLRN = PRN =1. [2 marks] Flip-flops to clear ( CLRN =0, PRN =1) Flip-flops to set ( CLRN =1, PRN =0) C A, B 27. Continue to develop the above counter that counts in the sequence (6 , 3 , 7 , 0 , 1) . What simplified SOP Boolean expression represents the appropriate combinational circuit if D flip-flops are used? [6 marks] BC A 00 01 11 10 0 1 BC A 00 01 11 10 0 1 BC A 00 01 11 10 0 1 Flip-Flop Input (same as Next State) Standard-Form Boolean Expression A ( t + 1) A ′ C B ( t + 1) A ′ C + AC ′ C ( t + 1) C ′ + A ′ B 11

ECE2277 Practice Final 28. Consider the following state diagram. 00 start 01 10 11 1/0 1/1 1/1 0/0 0/0 0/0 1/1 0/0 What type finite state machine (FSM) is this? [1 mark] (a) A Boole-type FSM. (b) A Mealy-type FSM. (c) A Moore-type FSM. (d) A Karnaugh-type FSM. b 29. Continue to work on the above FSM. Perform state reduction to simplify the state diagram. What is the minimum number of states and flip-flops required to implement the simplified machine? [2 marks] (a) The machine has 2 states and requires 2 flip-flops. (b) The machine has 2 states and requires 1 flip-flop. (c) The machine has 3 states and requires 2 flip-flops. (d) The machine has 4 states and requires 2 flip-flops. b 30. Continue working on the above FSM. What is the output for an input sequence 101100111000? Assume the machine starts in state 00 . [3 marks] (a) 001010001010. (b) 001010001111. (c) 001000100000. (d) 110111011111. c 12

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ECE2277 Practice Final 31. Continue working on the above FSM. Obtain the state table for the reduced machine. Please leave blank the rows for any states that have been eliminated in the reduced machine. When two (or more) states are equivalent, please remove the one with the higher number. [4 marks] State Input Next State Output 00 0 01 0 00 1 00 0 01 0 01 0 01 1 00 1 10 0 10 1 11 0 11 1 32. Consider a FSM with two states 0 and 1 , one input x , and one output y . The state table for this machine is: State A Input x Next State A ( t + 1) Output y 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 0 Obtain the standard-form Boolean expressions for the D input of flip-flop A and output y in terms of the current state A and input x . [4 marks] D = x ′ y = Ax ′ 33. Continue working with the two-state FSM from above. Instead of using a D flip-flop, implement this FSM with a T flip-flop by obtaining the Boolean expression for the input T based on the current state A and input x . [4 marks] T = Ax + A ′ x ′ 13