Lab1

Please be accurate otherwise I will lose my marks!!!!!!!

R R R Q S (a) (b) (c) For each circuit above, discuss whether or not the circuit has really the same behaviour as the RS latch. Hint: use NOR gate for the RS latch and then do the analysis.

No plagarism please! Correct and detailed answer will be Upvoted else downvoted. Thank you!

Q12: CSMA/CD is a protocol used in what Data Link Layer protocol? a. Polling b. Token Passing bus c. Token Passing ring d. Ethernet e. TDMA f. FDMA g. CDMA h. None of the above

Question II 1- Suppose AHU is allocated a block of IP address: 200.23.16.0/20. Based on your knowledge on IP addressing, answer the following questions: How many hosts at maximum can AHU supply with public IP addresses? Suppose there are 8 colleges that AHU needs to distribute the IP addresses to Suppose the IP address demand from each college is the same. What will be the block of IP addresses allocated to each college? How many hosts can each college supply with public IP addresses? (e) Suppose there are 6 colleges that AHU needs to distribute the IP addresses to. Two of the colleges request twice as much IP addresses as the other 4. What will be the block of IP addresses allocated to each college? How many hosts can each college supply with publie IP addresses?

Q3 /mention (3) main differences between TCP/IP AND OSI MODEL?

From the given circuit, derive the simplified NOR circuit and identify the TTL ICs in the design & its quantity. Don't forget to write the boolean expression which becomes the basis of the circuit construction

1. List TCP/IP Protocol layers with their functions and units for each one 2List types of addressing and the function for each address

can you drow a 5 bits johanson Counter ? with D filp flop.

%ar ull ? KB/S O 1:YY o Worksheet III .. Worksheet_III_2021 Q1: what's the decimal value of the binary 11011011 if the number implemented in: Sign and magnitude l's complement 2's complement Q2: For BCD code perform the following, with and without complement: 1. 1000010110 is subtracted from 10101000001. 2. 759 be subtracted from 645. Q3: If the given binary number 110101100 2 find the gray code and the decimal value of this Gray code. Q4: for 13-bit system find the following: • Number of total states • Range for signed numbers (positive and negative) Q5: perform the following operations in Hexadecimal (with and without complement): 7F + 9C 164 - 5E Q6: perform the following operations in Octal (with and without complement): 65 + 43 164 - 77 Q7: Find the following for a binary system: capable to represent a decimal number - 489 • Number of bits needed The Range for this system Q8: Write your full name: your first Name, Father and Grandfather in ASCII and show how many bytes needed to…

1- Which layers are network support layers? a. Physical Layer b. session Layer 2-What are the responsibilities of Data Link Layer? a. Framing b. Encryption c. Mail services 3- What are the types of errors? a. Compression b. Redundancy c. Single-Bit 4- What are the responsibilities of Application Layer? c. Application Layers Flow Control b. Translation c. Mail services 5- application layer protocols? a. TFTP b. ICMP c. (ARP)

How many NAND gates are required for implementing the function DD C O a. None of the above O b. 6 Ос. 4 O d. 3

This is a practice question (not a graded assignment) from my Digital Systems lab course. The first part was to create a schematic from 2:4 decoder truth table using only NAND gates. This was done, as you can see, and is correct. Now, we're supposed to write the VHDL code for a module named "2x4_Decoder" that implements the NAND gate schematic using gate terminology and the labels from the schematic, as well as a test bench for it. I'm completely lost. All we've done so far is simple individual gates, nothing with multiple gates or connections (it's our second week in VHDL). If I could see a complete, working example for this, I could probably figure out other implementation configurations. Thank you for your assistance.

Please draw the the circuit as well in the explanation and not only words/steps to construct and PLEASE DON'T POST ANY CHAT GPT ANSWERS.

Q17: Multiple Choice - In the TCP/IP version of the OSI Model, this helps to handle flow control, missing packets, and packets arriving out of order. a. TCP. b. MAC Addresses. c. Multiplexing. d. Encapsulation. e. NAT. f. MAC Frames g. None of the above.

Determine the radix r for the case: The circuit below is called__________. Full adder forms _________________________, but half-adder forms ___________________. The truth table for AND gate is: 14 pin TTL SSI chip can contain ___________ 3 input AND gates. Canonical form of a function’s representation can give us its _______ level implementation.

Which modulation scheme is used by Bluetooth? a) DQPSK b) MSK c) GFSK d) BPSK

Please do task as instructed .

b) Consider the below figure in which three hosts, with private IP addresses 10.0.1.12, 10.0.1.15, 10.0.1.18 are in a local network behind a router configured with NAT that sits between these three hosts and the larger Internet. IP datagrams being sent from, or destined to, these three hosts must pass through this NAT router. The router's interface on the LAN side has IP address 10.0.1.25, while the router's address on the Internet side has IP address 135.122.199.206. NAT translation table WAN side addr LAN side addr .1.. .1. D: S: D: D: .., .1. Suppose that the host with IP address 10.0.1.12 sends an IP datagram destined to host 128.119.180.182. The source port is 3376, and the destination port is 80. Find the source and destination IP addresses in packets at step 1,2, 3 and 4. Packet Source IP (S) Destination IP (D) 1 2 3

Please I need the answer as soon as possible pleeeeeeeaasse

What are the potential effects of "write amplification" on SSDs?

(a)A typical TTL IC is numbered as DM54AS04N.Explain the meaning of each portion of this number?- (b) What are types of scale of integration? Briefly explain VLSI?( (c)Draw the diagram of Monostable Multivibrator using 555 timer? -

Q.2) What is the method of arbitration of the PCI bus? Modify the following diagram arbitration, when there is a device C request use the PCI bus at the same time with device B. The arbiter services the device A then C to transfer 2 data for each, then service device B to transfer 1 data. CLK REOA REQ-S %3D GNTEA GNT-B %3D FRAME %3D %3D IRDY %3D TRDY Address Data Addre Data AD

Question 5: a) In the context of WCDMA, answer the following questions: What is the chip rate of WCDMA? i. ii. What is the duration for WCDMA frame? iii. For the figure shown below, what is the spreading factor? Symbol iv. V. vi. vii. Data Spreading code Spread signal Datax code Spreading What is the corresponding processing gain? For the figure shown below, what is the multiplexing mode used? Uplink Downlink Frequency Time WCDMA has a frequency reuse of 1 between different cells. What does that mean? If fast fading occurs when the path difference between two received signals is half wavelength. Calculate the path difference at a frequency equals to 2 GHz.