Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
3rd Edition
ISBN: 9780134123837
Author: Randal E. Bryant, David R. O'Hallaron
Publisher: PEARSON
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Textbook Question
Chapter 6, Problem 6.26HW
The following table gives the parameters for a number of different caches. Your task is to fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits.
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Q.1. Architecture performance [10 marks]
Answer
A certain microprocessor requires either 2, 4, or 6 machine cycles to perform various operations.
⚫ (40+g+f)% require 2 machine cycles,
⚫ (30-g) % require 4 machine cycles, and
⚫ (30-f)% require 6 machine cycles.
(a) What is the average number of machine cycles per instruction for this microprocessor?
Answer
(b) What is the clock rate (machine cycles per second) required for this microprocessor to be a
"1000 MIPS" processor?
Answer
(c) Suppose that 35% of the instructions require retrieving an operand from memory which
needs an extra 8 machine cycles. What is the average number of machine cycles per
instruction, including the instructions that fetch operands from memory?
Q.2. Architecture performance [25 marks]
Consider two different implementations, M1 and M2, of the same instruction set. M1 has a clock
rate of 2 GHz and M2 has a clock rate of 3.3 GHz. There are two classes of instructions with the
following CPIs:
Class
A
CPI for M1
CPI for M2
2.f
1.g
B
5
3
C
6
4
Note that the dots in 2 fand 1.g
indicate decimal points and not
multiplication.
a) What are the peak MIPS performances for both machines?
b) Which implementation is faster, if half the instructions executed in a certain program are from
class A, while the rest are divided equally among classes B and C.
c) What speedup factor for the execution of class-A instructions would lead to 20% overall
speedup?
d) What is the maximum possible speedup that can be achieved by only improving the execution
of class-A instructions? Explain why.
e) What is the clock rate required for microprocessor M1 to be a "1000 MIPS" (not peak MIPS)
processor?
PLEASE SOLVE STEP BY STEP WITHOUT ARTIFICIAL INTELLIGENCE OR CHATGPT
I don't understand why you use chatgpt, if I wanted to I would do it myself, I need to learn from you, not from being a d amn robot.
SOLVE STEP BY STEP I WANT THE DIAGRAM PERFECTLY IN SIMULINK
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective Plus Mastering Engineering With Pearson Etext -- Access Card Package (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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