Given Information : A 4-way set associative cache is given: Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A 1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02 2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E 3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2 4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA 5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A 6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1 FA 93 EB 48 7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30 The number of physical address bits is represented by “m”. The size of cache represented is by “C”. The block of size in bytes is represented as “B”. Associativity is represented as “E”. The number of cache sets is represented by “S”. The number of tag bits is represented by “t”. The number of block offset bits is represented as “b”.

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Answer 1

Question

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

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Q.1. Architecture performance [10 marks] Answer A certain microprocessor requires either 2, 4, or 6 machine cycles to perform various operations. ⚫ (40+g+f)% require 2 machine cycles, ⚫ (30-g) % require 4 machine cycles, and ⚫ (30-f)% require 6 machine cycles. (a) What is the average number of machine cycles per instruction for this microprocessor? Answer (b) What is the clock rate (machine cycles per second) required for this microprocessor to be a "1000 MIPS" processor? Answer (c) Suppose that 35% of the instructions require retrieving an operand from memory which needs an extra 8 machine cycles. What is the average number of machine cycles per instruction, including the instructions that fetch operands from memory?

Q.2. Architecture performance [25 marks] Consider two different implementations, M1 and M2, of the same instruction set. M1 has a clock rate of 2 GHz and M2 has a clock rate of 3.3 GHz. There are two classes of instructions with the following CPIs: Class A CPI for M1 CPI for M2 2.f 1.g B 5 3 C 6 4 Note that the dots in 2 fand 1.g indicate decimal points and not multiplication. a) What are the peak MIPS performances for both machines? b) Which implementation is faster, if half the instructions executed in a certain program are from class A, while the rest are divided equally among classes B and C. c) What speedup factor for the execution of class-A instructions would lead to 20% overall speedup? d) What is the maximum possible speedup that can be achieved by only improving the execution of class-A instructions? Explain why. e) What is the clock rate required for microprocessor M1 to be a "1000 MIPS" (not peak MIPS) processor?

Answer 2

Question

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

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Answer 3

Question

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

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Answer 4

Question

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

Expert Solution & Answer

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Answer 5

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

Answer 6

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

Answer 7

Chapter 6, Problem 6.33HW

Program Plan Intro

Given Information:

A 4-way set associative cache is given:

Index Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3 Tag V Bytes 0-3
0 F0 1 ED 32 0A A2 8A 1 BF 80 1D FC 14 1 EF 09 86 2A BC 0 25 44 6F 1A
1 BC 0 03 3E CD 38 A0 0 16 7B ED 5A BC 1 8E 4C DF 18 E4 1 FB B7 12 02
2 BC 1 54 9E 1E FA B6 1 DC 81 B2 14 00 0 B6 1F 7B 44 74 0 10 F5 B8 2E
3 BE 0 2F 7E 3D A8 C0 1 27 95 A4 74 C4 0 07 11 6B D8 BC 0 C7 B7 AF C2
4 7E 1 32 21 1C 2C 8A 1 22 C2 DC 34 BC 1 BA DD 37 D8 DC 0 E7 A2 39 BA
5 98 0 A9 76 2B EE 54 0 BC 91 D5 92 98 1 80 BA 9B F6 BC 1 48 16 81 0A
6 38 0 5D 4D F7 DA BC 1 69 C2 8C 74 8A 1 A8 CE 7F DA 38 1
FA 93

EB 48
7 8A 1 04 2A 32 6A 9E 0 B1 86 56 0E CC 1 96 30 47 F2 BC 1 F8 1D 42 30

The number of physical address bits is represented by “m”.

The size of cache represented is by “C”.

The block of size in bytes is represented as “B”.

Associativity is represented as “E”.

The number of cache sets is represented by “S”.

The number of tag bits is represented by “t”.

The number of block offset bits is represented as “b”.

Answer 8

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Answer 9

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Answer 10

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Answer 11

Ch. 6.1 - Prob. 6.1PP Ch. 6.1 - Prob. 6.2PP Ch. 6.1 - Prob. 6.3PP Ch. 6.1 - Prob. 6.4PP Ch. 6.1 - Prob. 6.5PP Ch. 6.1 - Prob. 6.6PP Ch. 6.2 - Prob. 6.7PP Ch. 6.2 - Prob. 6.8PP Ch. 6.4 - Prob. 6.9PP Ch. 6.4 - Prob. 6.10PP

Solution Summary: The author explains that a 4-way set associative cache is given. The number of physical address bits is represented by "m".

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Chapter 6 Solutions

Index	Tag	V	Bytes 0-3	Tag	V	Bytes 0-3	Tag	V	Bytes 0-3	Tag	V	Bytes 0-3
0	F0	1	ED 32 0A A2	8A	1	BF 80 1D FC	14	1	EF 09 86 2A	BC	0	25 44 6F 1A
1	BC	0	03 3E CD 38	A0	0	16 7B ED 5A	BC	1	8E 4C DF 18	E4	1	FB B7 12 02
2	BC	1	54 9E 1E FA	B6	1	DC 81 B2 14	00	0	B6 1F 7B 44	74	0	10 F5 B8 2E
3	BE	0	2F 7E 3D A8	C0	1	27 95 A4 74	C4	0	07 11 6B D8	BC	0	C7 B7 AF C2
4	7E	1	32 21 1C 2C	8A	1	22 C2 DC 34	BC	1	BA DD 37 D8	DC	0	E7 A2 39 BA
5	98	0	A9 76 2B EE	54	0	BC 91 D5 92	98	1	80 BA 9B F6	BC	1	48 16 81 0A
6	38	0	5D 4D F7 DA	BC	1	69 C2 8C 74	8A	1	A8 CE 7F DA	38	1	FA 93 EB 48
7	8A	1	04 2A 32 6A	9E	0	B1 86 56 0E	CC	1	96 30 47 F2	BC	1	F8 1D 42 30