Chapter 5, Problem D5.88DP

Consider a common−emitter circuit with the configuration shown in Figure 5.54(a). Assume a bias voltage of $V_{CC}=3.3\text{V}$ and assume the transistor current gain is in the range $100\le \beta \le 160$ . Design the circuit such that the nominal Q−point is in the center of the load line and that the Q−point values do not vary by more than $\pm 3$ percent. Determine appropriate values for $R_1$ and $R_2$ .