MICROELECT. CIRCUIT ANALYSIS&DESIGN (LL)
4th Edition
ISBN: 9781266368622
Author: NEAMEN
Publisher: MCG
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Textbook Question
Chapter 5, Problem 12RQ
Describe a bipolar transistor NOR logic circuit.
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Students have asked these similar questions
Create the PLC ladder logic diagram
for the logic gate circuit displayed in
Figure 7-35. The pilot light red (PLTR)
output section has three inputs: PBR,
PBG, and SW. Pushbutton red (PBR)
and pushbutton green (PBG) are inputs
to an XOR logic gate. The output of the
XOR logic gate and the inverted switch
SW) are inputs to a two-input AND
logic gate. These inputs generate the
pilot light red (PLTR) output.
The two-input AND logic gate output
is also fed into a two-input NAND logic
PBR
PBG
SW
TSW
PLTR
Figure 7-35. Logic gate circuit for Example 7-3.
PLTW
Goodheart-Willcox Publisher
gate. The temperature switch (TSW) is the other input to the NAND logic gate. The output generated from
the NAND logic gate is labeled pilot light white (PLTW).
Imaginary Axis (seconds)
1
6. Root locus for a closed-loop system with L(s) =
is shown below.
s(s+4)(s+6)
15
10-
0.89
0.95
0.988
0.988
-10
0.95
-15
-25
0.89
20
Root Locus
0.81
0.7
0.56
0.38
0.2
5
10
15
System: sys
Gain: 239
Pole: -0.00417 +4.89
Damping: 0.000854
Overshoot (%): 99.7
Frequency (rad/s): 4.89
System: sys
Gain: 16.9
Pole: -1.57
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 1.57
0.81
0.7
0.56
0.38
0.2
-20
-15
-10
-5
5
10
Real Axis (seconds)
From the values shown in the figure, compute the following.
a) Range of K for which the closed-loop system is stable.
b) Range of K for which the closed-loop step response will not have any overshoot.
Note that when all poles are real, the step response has no overshoot.
c) Smallest possible peak time of the system. Note that peak time is the smallest
when wa is the largest for the dominant pole.
d) Smallest possible settling time of the system. Note that peak time is the smallest
when σ is the largest for the dominant pole.
For a band-rejection filter, the response drops below this half power point at two locations as visualised in Figure 7, we need to find these
frequencies. Let's call the lower frequency-3dB point as fr and the higher frequency -3dB point fH. We can then find out the bandwidth as
f=fHfL, as illustrated in Figure 7.
0dB
Af
-3 dB
Figure 7. Band reject filter response diagram
Considering your AC simulation frequency response and referring to Figure 7, measure the following from your AC simulation. 1% accuracy:
(a) Upper-3db Frequency (fH) =
Hz
(b) Lower-3db Frequency (fL) =
Hz
(c) Bandwidth (Aƒ) =
Hz
(d) Quality Factor (Q) =
Chapter 5 Solutions
MICROELECT. CIRCUIT ANALYSIS&DESIGN (LL)
Ch. 5 - An npn transistor is biased in the forwardactive...Ch. 5 - (a) The common-emitter current gains of two...Ch. 5 - An npn transistor is biased in the forwardactive...Ch. 5 - The emitter current in a pnp transistor biased in...Ch. 5 - The output resistance of a bipolar transistor is...Ch. 5 - Assume that IC=1mA at VCE=1V , and that VBE is...Ch. 5 - The openemitter breakdown voltage is BVCBO=200V ,...Ch. 5 - A particular transistor circuit requires a minimum...Ch. 5 - The circuit elements in Figure 5.20(a) are changed...Ch. 5 - The circuit elements in Figure 5.22(a) are V+=3.3V...
Ch. 5 - (a) Verify the results of Example 5.3 with a...Ch. 5 - Consider the pnp circuit in Figure 5.22(a). Assume...Ch. 5 - In the following exercise problems, assume...Ch. 5 - In the following exercise problems, assume...Ch. 5 - The circuit elements in Figure 5.27(a) are changed...Ch. 5 - Using a PSpice simulation, plot the voltage...Ch. 5 - The parameters of the circuit shown in Figure...Ch. 5 - Design the commonbase circuit shown in Figure 5.33...Ch. 5 - The bias voltages in the circuit shown in Figure...Ch. 5 - The bias voltages in the circuit shown in Figure...Ch. 5 - The circuit elements in Figure 5.36(a) are V+=5V ,...Ch. 5 - For the transistor shown in the circuit of Figure...Ch. 5 - For the circuit shown in Figure 5.41, determine...Ch. 5 - Assume =120 for the transistor in Figure 5.42....Ch. 5 - For the transistor in Figure 5.43, assume =90 ....Ch. 5 - (a) Redesign the LED circuit in Figure 5.45(a)...Ch. 5 - The transistor parameters in the circuit in Figure...Ch. 5 - Redesign the inverter amplifier circuit shown in...Ch. 5 - For the circuit shown in Figure 5.44, assume...Ch. 5 - Consider the circuit shown in Figure 5.51(b)....Ch. 5 - [Note: In the following exercises, assume the BE...Ch. 5 - [Note: In the following exercises, assume the B—E...Ch. 5 - Consider the circuit in Figure 5.54(a), let...Ch. 5 - Prob. 5.16EPCh. 5 - The parameters of the circuit shown in Figure...Ch. 5 - Consider the circuit in Figure 5.54(a). The...Ch. 5 - Consider the circuit shown in Figure 5.58. The...Ch. 5 - In the circuit shown in Figure 5.60, the...Ch. 5 - The parameters of the circuit shown in Figure...Ch. 5 - For Figure 5.59, the circuit parameters are...Ch. 5 - In the circuit shown in Figure 5.61, determine new...Ch. 5 - For the circuit shown in Figure 5.63, the circuit...Ch. 5 - (a) Verily the cascode circuit design in Example...Ch. 5 - Prob. 1RQCh. 5 - Prob. 2RQCh. 5 - Prob. 3RQCh. 5 - Define commonbase current gain and commonemitter...Ch. 5 - Discuss the difference between the ac and dc...Ch. 5 - State the relationships between collector,...Ch. 5 - Define Early voltage and collector output...Ch. 5 - Describe a simple commonemitter circuit with an...Ch. 5 - Prob. 9RQCh. 5 - Prob. 10RQCh. 5 - Prob. 11RQCh. 5 - Describe a bipolar transistor NOR logic circuit.Ch. 5 - Describe how a transistor can be used to amplify a...Ch. 5 - Discuss the advantages of using resistor voltage...Ch. 5 - Prob. 15RQCh. 5 - Prob. 16RQCh. 5 - (a) In a bipolar transistor biased in the...Ch. 5 - (a) A bipolar transistor is biased in the...Ch. 5 - (a) The range of ( for a particular type of...Ch. 5 - (a) A bipolar transistor is biased in the...Ch. 5 - Prob. 5.5PCh. 5 - An npn transistor with =80 is connected in a...Ch. 5 - Prob. 5.7PCh. 5 - A pnp transistor with =60 is connected in a...Ch. 5 - (a) The pnp transistor shown in Figure P5.8 has a...Ch. 5 - An npn transistor has a reverse-saturation current...Ch. 5 - Two pnp transistors, fabricated with the same...Ch. 5 - The collector currents in two transistors, A and...Ch. 5 - Prob. 5.13PCh. 5 - Prob. 5.14PCh. 5 - In a particular circuit application, the minimum...Ch. 5 - A particular transistor circuit design requires a...Ch. 5 - For all the transistors in Figure P5.17, =75 . The...Ch. 5 - The emitter resistor values in the circuits show...Ch. 5 - Consider the two circuits in Figure P5.19. The...Ch. 5 - The current gain for each transistor in the...Ch. 5 - Consider the circuits in Figure P5.21. For each...Ch. 5 - (a) The circuit and transistor parameters for the...Ch. 5 - In the circuits shown in Figure P5.23, the values...Ch. 5 - (a) For the circuit in Figure P5.24, determine VB...Ch. 5 - (a) The bias voltages in the circuit shown in...Ch. 5 - The transistor shown in Figure P5.26 has =120 ....Ch. 5 - The transistor in the circuit shown in Figure...Ch. 5 - In the circuit in Figure P5.27, the constant...Ch. 5 - For the circuit shown in Figure P5.29, if =200 for...Ch. 5 - The circuit shown in Figure P5.30 is to be...Ch. 5 - (a) The bias voltage in the circuit in Figure P5.3...Ch. 5 - The current gain of the transistor in the circuit...Ch. 5 - (a) The current gain of the transistor in Figure...Ch. 5 - (a) The transistor shown in Figure P5.34 has =100...Ch. 5 - Assume =120 for the transistor in the circuit...Ch. 5 - For the circuit shown in Figure P5.27, calculate...Ch. 5 - Consider the commonbase circuit shown in Figure...Ch. 5 - (a) For the transistor in Figure P5.38, =80 ....Ch. 5 - Let =25 for the transistor in the circuit shown in...Ch. 5 - (a) The circuit shown in Figure P5.40 is to be...Ch. 5 - The circuit shown in Figure P5.41 is sometimes...Ch. 5 - The transistor in Figure P5.42 has =120 . (a)...Ch. 5 - The commonemitter current gain of the transistor...Ch. 5 - For the circuit shown in Figure P5.44, plot the...Ch. 5 - The transistor in the circuit shown in Figure...Ch. 5 - Consider the circuit in Figure P5.46. For the...Ch. 5 - The current gain for the transistor in the circuit...Ch. 5 - Consider the amplifier circuit shown in Figure...Ch. 5 - For the transistor in the circuit shown in Figure...Ch. 5 - Reconsider Figure P5.49. The transistor current...Ch. 5 - The current gain of the transistor shown in the...Ch. 5 - For the circuit shown in Figure P5.52, let =125 ....Ch. 5 - Consider the circuit shown in Figure P5.53. (a)...Ch. 5 - (a) Redesign the circuit shown in Figure P5.49...Ch. 5 - Prob. 5.55PCh. 5 - Consider the circuit shown in Figure P5.56. (a)...Ch. 5 - (a) Determine the Q-point values for the circuit...Ch. 5 - (a) Determine the Q-point values for the circuit...Ch. 5 - (a) For the circuit shown in Figure P5.59, design...Ch. 5 - Design a bias-stable circuit in the form of Figure...Ch. 5 - Using the circuit in Figure P5.61, design a...Ch. 5 - For the circuit shown in Figure P5.61, the bias...Ch. 5 - (a) A bias-stable circuit with the configuration...Ch. 5 - (a) For the circuit shown in Figure P5.64, assume...Ch. 5 - The dc load line and Q-point of the circuit in...Ch. 5 - The range of ß for the transistor in the circuit...Ch. 5 - The nominal Q-point of the circuit in Figure P5.67...Ch. 5 - (a) For the circuit in Figure P5.67, the value of...Ch. 5 - For the circuit in Figure P5.69, let =100 and...Ch. 5 - Prob. 5.70PCh. 5 - Design the circuit in Figure P5.70 to be bias...Ch. 5 - Consider the circuit shown in Figure P5.72. (a)...Ch. 5 - For the circuit in Figure P5.73, let =100 . (a)...Ch. 5 - Prob. D5.74PCh. 5 - (a) Design a fourresistor bias network with the...Ch. 5 - (a) Design a four-resistor bias network with the...Ch. 5 - (a) A fourresistor bias network is to be designed...Ch. 5 - (a) Design a fourresistor bias network with the...Ch. 5 - For each transistor in the circuit in Figure...Ch. 5 - The parameters for each transistor in the circuit...Ch. 5 - The bias voltage in the circuit shown in Figure...Ch. 5 - Consider the circuit shown in Figure P5.82. The...Ch. 5 - (a) For the transistors in the circuit shown in...Ch. 5 - Using a computer simulation, plot VCE versus V1...Ch. 5 - Using a computer simulation, verify the results of...Ch. 5 - Using a computer simulation, verify the results of...Ch. 5 - Consider a commonemitter circuit with the...Ch. 5 - The emitterfollower circuit shown in Figure P5.89...Ch. 5 - The bias voltages for the circuit in Figure...Ch. 5 - The multitransistor circuit in Figure 5.61 is to...
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- my previous answers for a,b,d were wrong a = 1050 b = 950 d=9.99 c was the only correct value i got previously c = 100hz is correctarrow_forwardV₁(t) ww ZRI ZLI ZL2 ZTH Zci VTH Zc21 Figure 8. Circuit diagram showing calculation approach for VTH and Z TH we want to create a blackbox for the red region, we want to use the same input signal conditions as previously the design of your interference ector circuit: Sine wave with a 1 Vpp, with a frequency of 100 kHz (interference) Square wave with 2.4Vpp, with a frequency of 10 kHz (signal) member an AC Thevenin equivalent is only valid at one frequency. We have chosen to calculate the Thevenin equivalent circuit (and therefore the ackbox) at the interference frequency (i.e. 100 kHz), and the signal frequency (i.e. 10 kHz) as these are the key frequencies to analyse. Your boss is assured you that the waveform converter module has been pre-optimised to the DAB Receiver if you use the recommended circuit topology.arrow_forwardVs(t) + v(t) + vi(t) ZR ZL Figure 1: Second order RLC circuit Zc + ve(t) You are requested to design the circuit shown in Figure 1. The circuit is assumed to be operating at its resonant frequency when it is fed by a sinusoidal voltage source Vs (t) = 2sin(le6t). To help design your circuit you have been given the value of inductive reactance ZL = j1000. Assume that the amplitude of the current at resonance is Is (t) = 2 mA. Based on this information, answer the following to help design your circuit. Use cartesian notation for your answers, where required.arrow_forward
- What is the attenuation at the resonant frequency? You should use the LTSpice cursors for your measurement. Answer to within 1% accuracy, or enter 0, or infinity (as "inf") (a) Attenuation (dB) = dB Check You may have noticed that it was significantly easier to use frequency-domain "AC" simulation to measure the attenuation, compared to the steps we performed in the last few questions. (i.e. via a time-domain "transient" simulation). AC analysis allows us to observe and quantify large scale positive or negative changes in a signal of interest across a wide range of different frequencies. From the response you will notice that only frequencies that are relatively close to 100 kHz have been attenuated. This is the result of the Band-reject filter you have designed, and shows the 'rejection' (aka attenuation) of any frequencies that lie in a given band. The obvious follow-up question is how do we define this band? We use a quantity known as the bandwidth. A commonly used measurement for…arrow_forwardV₁(t) ww ZRI ZLI ZL2 ZTH Zci VTH Zc21 Figure 8. Circuit diagram showing calculation approach for VTH and Z TH we want to create a blackbox for the red region, we want to use the same input signal conditions as previously the design of your interference ector circuit: Sine wave with a 1 Vpp, with a frequency of 100 kHz (interference) Square wave with 2.4Vpp, with a frequency of 10 kHz (signal) member an AC Thevenin equivalent is only valid at one frequency. We have chosen to calculate the Thevenin equivalent circuit (and therefore the ackbox) at the interference frequency (i.e. 100 kHz), and the signal frequency (i.e. 10 kHz) as these are the key frequencies to analyse. Your boss is assured you that the waveform converter module has been pre-optimised to the DAB Receiver if you use the recommended circuit topology.arrow_forwardVs(t) + v(t) + vi(t) ZR ZL Figure 1: Second order RLC circuit Zc + ve(t) You are requested to design the circuit shown in Figure 1. The circuit is assumed to be operating at its resonant frequency when it is fed by a sinusoidal voltage source Vs (t) = 2sin(le6t). To help design your circuit you have been given the value of inductive reactance ZL = j1000. Assume that the amplitude of the current at resonance is Is (t) = 2 mA. Based on this information, answer the following to help design your circuit. Use cartesian notation for your answers, where required.arrow_forward
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