Computer Science: An Overview (13th Edition) (What's New in Computer Science)
13th Edition
ISBN: 9780134875460
Author: Glenn Brookshear, Dennis Brylow
Publisher: PEARSON
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Chapter 3.5, Problem 2QE
Program Plan Intro
Privileged levels:
The privilege levels control the access of the program executing in real time on the
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Modern 64-bit Processors with 64-bit address buses may access a maximum of 264 bytes of memory. Do you think the need for virtual memory would disappear if sufficient physical memory could be provided in these systems at a reasonable price? Argue your point of view.
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As a simple model of a bus-based multiprocessor system without caching, suppose that one instruction in every four references memory, and that a memory reference occupies the bus for an entire instruction time. If the bus is busy, the requesting CPU is put into a FIFO queue. How much faster will a 64-CPU system run than a 1-CPU system?
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Chapter 3 Solutions
Computer Science: An Overview (13th Edition) (What's New in Computer Science)
Ch. 3.1 - Identify examples of queues. In each case,...Ch. 3.1 - Which of the following activities require...Ch. 3.1 - Prob. 3QECh. 3.1 - Prob. 4QECh. 3.2 - Prob. 1QECh. 3.2 - What is the difference between application...Ch. 3.2 - Prob. 3QECh. 3.2 - Prob. 4QECh. 3.3 - Summarize the difference between a program and a...Ch. 3.3 - Summarize the steps performed by the CPU when an...
Ch. 3.3 - Prob. 3QECh. 3.3 - If each time slice in a multiprogramming system is...Ch. 3.3 - Prob. 5QECh. 3.4 - Prob. 1QECh. 3.4 - Suppose a two-lane road converges to one lane to...Ch. 3.4 - Prob. 3QECh. 3.4 - Prob. 4QECh. 3.5 - Prob. 1QECh. 3.5 - Prob. 2QECh. 3.5 - If a process in a multiprogramming system could...Ch. 3 - List four activities of a typical operating...Ch. 3 - Summarize the distinction between batch processing...Ch. 3 - Prob. 3CRPCh. 3 - Prob. 4CRPCh. 3 - What is a multitasking operating system?Ch. 3 - Prob. 6CRPCh. 3 - On the basis of a computer system with which you...Ch. 3 - a. What is the role of the user interface of an...Ch. 3 - What directory structure is described by the path...Ch. 3 - Define the term process as it is used in the...Ch. 3 - Prob. 11CRPCh. 3 - What is the difference between a process that is...Ch. 3 - What is the difference between virtual memory and...Ch. 3 - Suppose a computer contained 512MB (MiB) of main...Ch. 3 - What complications could arise in a...Ch. 3 - What is the distinction between application...Ch. 3 - Prob. 17CRPCh. 3 - Summarize the booting process.Ch. 3 - Why is the booting process necessary?Ch. 3 - If you have a PC, record the sequence activities...Ch. 3 - Suppose a multiprogramming operating system...Ch. 3 - Prob. 22CRPCh. 3 - Prob. 23CRPCh. 3 - Prob. 24CRPCh. 3 - Prob. 25CRPCh. 3 - Would greater throughput be achieved by a system...Ch. 3 - Prob. 27CRPCh. 3 - What information is contained in the state of a...Ch. 3 - Identify a situation in a multiprogramming system...Ch. 3 - List in chronological order the major events that...Ch. 3 - Prob. 31CRPCh. 3 - Prob. 32CRPCh. 3 - Explain an important use for the test-and-set...Ch. 3 - Prob. 34CRPCh. 3 - Prob. 35CRPCh. 3 - Prob. 36CRPCh. 3 - Prob. 37CRPCh. 3 - Each of two robot arms is programmed to lift...Ch. 3 - Prob. 39CRPCh. 3 - Prob. 40CRPCh. 3 - Prob. 41CRPCh. 3 - Prob. 42CRPCh. 3 - Prob. 43CRPCh. 3 - Prob. 44CRPCh. 3 - Prob. 45CRPCh. 3 - Prob. 46CRPCh. 3 - Prob. 47CRPCh. 3 - Prob. 48CRPCh. 3 - Prob. 49CRPCh. 3 - Prob. 50CRPCh. 3 - Prob. 51CRPCh. 3 - Prob. 52CRPCh. 3 - How is the window manager related to the operating...Ch. 3 - Prob. 54CRPCh. 3 - Prob. 55CRPCh. 3 - Suppose you are using a multiuser operating system...Ch. 3 - Prob. 2SICh. 3 - Prob. 3SICh. 3 - Prob. 4SICh. 3 - Prob. 5SI
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- Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?arrow_forwardThe MSP430X family (X stands for eXtended) can handle a larger amount of memory since it has a 20-bit wide address bus. This family of processors is built based on a von Neumann architecture and is byte-addressed as well. What is the maximum number of bytes that can be addressed? Enter a decimal value.arrow_forwardA read/write type memory will be designed for a microprocessor with 16 bit address bus.. Memory chips will be 1K type. Write down bitwise memory addresses for each chip and determine address bits for S0=, S1= and I0=, I1=, I2= and I3= for which memory chip. Draw the full system architecture (CPU-Memory-Decoder-Buses). Write your name on, Student Id and put signature on the paper and take full picture If your last digit of your Student ID is 0, 2,5 then memory range $1C00H-27FFH If your last digit of your Student ID is 1, 3, 6, 9 then memory range $2400H-33FFH If your last digit of your Student ID is 4, 7 , 8 then memory range $3800H-43FFH LAST DİGİT = 9arrow_forward
- A multiprocessor has a 3.3 GHz clock (0.3 nsec) and CPI = 0.7 when references are satisfied by the local cache. How much faster is an application which uses only local references versus when 2% of the references are remote the processor stall for the remote access is 200nsec ?arrow_forwardConsider a computer system that contains an I/O module controlling a simple keyboard/printer teletype. The following registers are contained in the processor and connected directly to the system bus: INPR: Input register – 8 bits OUTR: Output register – 8 bits FGI: Input flag – 1 bit FGO: Output flag – 1 bit IEN: Interrupt enable – 1 bit Keystroke input from the teletype and printer output to the teletype are controlled by the I/O module. The teletype is able to encode an alphanumeric symbol to an 8-bit word and decode an 8-bit word into an alphanumeric symbol. Describe how the processor, using the first four registers listed in the problem can achieve I/O with the teletype. Describe how the function can be performed more efficiently by also employing IEN.arrow_forwardConsider a computer with a single off-chip cache with a 10 ns hit time and a 95% hit rate. Mainmemory has an access time of 80 ns.I. What is the computer’s effective memory access time?II. Now, suppose, If we add a small on-chip direct mapped cache with a 1.4 ns hit time with60% hit rate, what is the computer’s effective memory access time?III. An alternative is to add a slightly larger 2-way associative on-chip cache with 2.1 ns hittime with 90% hit rate, what is the computer’s effective memory access time? IV. Which of the two alternatives is better? Determine the speedup achieved by the twoon-chip cache configurations (w.r.t. the baseline off-chip only cache)?arrow_forward
- Let's pretend that the number of usable cores in central processing units (CPUs) is doubled every 18 months. In order to maintain the current level of per-core performance, how much more off-chip memory bandwidth would a CPU launched in three years need?arrow_forwardConsider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock fre- quency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.arrow_forward264 bytes of memory may be referenced by current 64-bit CPUs with 64-bit address buses. Do you believe that the requirement for virtual memory would be abolished if adequate physical memory could be cost effectively added in these systems? Make your case for or against.arrow_forward
- Let's pretend that the number of usable cores in central processing units (CPUs) is doubled every 18 months. How much more off-chip memory bandwidth would a CPU released in three years need in order to maintain the same per-core performance?arrow_forwardFor a microprocessor 68000 Motorola system, how many memory addresses which can be accessed by it? Prove it and justify the last address of the memory location. Then, sketch the memory map of it by using the address calculated.arrow_forwardA 32-bit microprocessor with the same bus cycle as a 16-bit microprocessor is an example of this. If 20% of the operands and instructions are 32 bits long, 40% are 16 bits long, and 40% are just 8 bits long, then the problem will be solved. Calculate the benefit of using a 32-bit CPU when retrieving instructions and operands.arrow_forward
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