Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
Write HCL code for the signal D_stall in the PIPE implementation.Pipeline register D must be set to bubble for a mispredicted branch ora ret instruction. As the analysis in the preceding section shows,however, it should not inject a bubble when there is a load/use hazardin combination with a ret instruction:bool D_bubble =# Mispredicted branch (E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA,d_srcB }) && IRET in { D_icode, E_icode, M_icode };

Write HCL code for the signal D_stall in the PIPE implementation.Pipeline register D must be set to bubble for a mispredicted branch ora ret instruction. As the analysis in the preceding section shows,however, it should not inject a bubble when there is a load/use hazardin combination with a ret instruction:bool D_bubble =# Mispredicted branch (E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA,d_srcB }) && IRET in { D_icode, E_icode, M_icode };

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question

Write HCL code for the signal D_stall in the PIPE implementation.
Pipeline register D must be set to bubble for a mispredicted branch or
a ret instruction. As the analysis in the preceding section shows,
however, it should not inject a bubble when there is a load/use hazard
in combination with a ret instruction:
bool D_bubble =
# Mispredicted branch (E_icode == IJXX && !e_Cnd) ||
# Stalling at fetch while ret passes through pipeline
# but not condition for a load/use hazard
!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA,
d_srcB }) && IRET in { D_icode, E_icode, M_icode };

Expert Solution
steps

Step by step

Solved in 2 steps

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS