use IEEE.STD_LOGIC_1164.ALL; entity VHDL_MOORE_FSM is port ( clock: in std_logic; --- clock signal reset: in std_logic; -- active high async reset input X : in std_logic; -- binary sequence input Z : out std_logic -- output of the VHDL FSM ); end VHDL_MOORE_FSM; architecture Behavioral of
Given the VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VHDL_MOORE_FSM is
port ( clock: in std_logic; --- clock signal
reset: in std_logic; -- active high async reset input
X : in std_logic; -- binary sequence input
Z : out std_logic -- output of the VHDL FSM
);
end VHDL_MOORE_FSM;
architecture Behavioral of VHDL_MOORE_FSM is
type MOORE_FSM is (S0,S1,S2,S3,S4);
signal current_state, next_state: MOORE_FSM;
begin
-- Sequential memory of the VHDL MOORE FSM
process(clock,reset)
begin
if(reset='1') then
current_state <= S0; --initial state considered as S0
elsif(rising_edge(clock)) then
current_state <= next_state;
end if;
end process;
-- Next state logic of the VHDL MOORE FSM Sequence Detector
-- Combinational logic
process(current_state,X)
begin
case(current_state) is
when S0=>
if(X='1') then -- "1"
next_state <= S1;
else
next_state <= S0;
end if;
when S1 =>
if(X='1') then -- "1"
next_state <= S3;
else
next_state <= S2;
end if;
when S2 =>
if(X='1') then -- "1"
next_state <= S2;
else
next_state <= S4;
end if;
when S3 =>
if(X='1') then -- "1"
next_state <= S2;
else
next_state <= S4;
end if;
when S4=>
next_state <= S0;
when others => next_state <= S0;
end case;
end process;
-- Output logic of the VHDL MOORE FSM
process(current_state)
begin
case current_state is
when S0 => Z <= '0';
when S1 => Z <= '0';
when S2 => Z <= '0';
when S3 => Z <= '0';
when S4 => Z <= '1';
when others => Z <= '0';
end case;
end process;
end Behavioral;
Question: Write a TEST BENCH for this VHDL code. Add a SLOW CLOCK to the code.
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