Write a Test Bench for the Five-Cycles High Laser Timer (please see the VHDL code for reference).
Write a Test Bench for the Five-Cycles High Laser Timer (please see the VHDL code for reference).
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Question
Write a Test Bench for the Five-Cycles High Laser Timer (please see the VHDL code for reference).

Transcribed Image Text:library ieee;
use ieee.std logic l164.all;
entity LaserTimer is
port (b : in std logic;
x : out std logic;
clk, rst : in std logic -- Tclk = 10 ns
6.
-- output = 50 ns
7
8
end LaserTimer;
10
11
architecture behavior of LaserTimer is
12
type statetype is
(S_Off, s_Onl, s_On2, s_On3, s_On4, s_On5);
signal currentState, nextState: statetype;
13
14
15
16
begin
17
statereg: process (clk, rst)
18
begin
19
if (rst='l') then
initial state
--
20
currentstate <= S Off;
21
elsif (clk='1' and clk'event) then
22
currentstate <= nextstate;
23
end if;
24
end process;
26
comblogic: process (currentstate, b)
27
begin
28
case currentstate is
29
when S Off =>
x <= '0';
if (b=' 0') then
nextstate <= S Off;
30
laser off
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else
34
nextstate <= S Onl;
35
end if;
36
when S Onl =>
x <= '1';
nextstate <= s On2;
37
laser on
--
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when S On2 =>
40
x <= 'l';
laser on
--
41
nextstate <= S On3;
42
when S On3 =>
43
x <= '1';
laser on
--
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nextstate <= S On4;
45
when S On4 =>
x <= '1';
nextstate <= S On5;
46
laser on
--
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when S On5 =>
x <= '1';
nextstate <= S Off;
end case;
49
laser on
--
50
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end process;
53
end behavior;
54
2222 N M M m m m m m 3
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