Question: Given the VHDL code for a 16-to-1 Multiplexer, please provide a Test Bench file. VHDL Code for a 16-to-1 Multiplexer: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux16to1 is Port ( w0 : in STD_LOGIC; w1 : in STD_LOGIC; w2 : in STD_LOGIC; w3 : in STD_LOGIC; w4 : in STD_LOGIC; w5 : in STD_LOGIC; w6 : in STD_LOGIC; w7 : in STD_LOGIC; w8 : in STD_LOGIC; w9 : in STD_LOGIC; w10 : in STD_LOGIC; w11 : in STD_LOGIC; s : in STD_LOGIC_VECTOR(3 DOWNTO 0); f : out STD_LOGIC); end mux16to1; architecture Behavioral of mux16to1 is begin process (s) begin case s is when "0000" => f <= w0 when "0001" => f <= w1 when "0010" => f <= w2 when "0011" => f <= w3 when "0100" => f <= w4 when "0101" => f <= w5 when "0110" => f <= w6 when "0111" => f <= w7 when "1000" => f <= w8 when "1001" => f <= w9 when "1010" => f <= w10 when "1011" => f <= w11 when others => f <= 'z'; end case end process end Behavioral;

Question: Given the VHDL code for a 16-to-1 Multiplexer, please provide a Test Bench file. VHDL Code for a 16-to-1 Multiplexer: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux16to1 is Port ( w0 : in STD_LOGIC; w1 : in STD_LOGIC; w2 : in STD_LOGIC; w3 : in STD_LOGIC; w4 : in STD_LOGIC; w5 : in STD_LOGIC; w6 : in STD_LOGIC; w7 : in STD_LOGIC; w8 : in STD_LOGIC; w9 : in STD_LOGIC; w10 : in STD_LOGIC; w11 : in STD_LOGIC; s : in STD_LOGIC_VECTOR(3 DOWNTO 0); f : out STD_LOGIC); end mux16to1; architecture Behavioral of mux16to1 is begin process (s) begin case s is when "0000" => f <= w0 when "0001" => f <= w1 when "0010" => f <= w2 when "0011" => f <= w3 when "0100" => f <= w4 when "0101" => f <= w5 when "0110" => f <= w6 when "0111" => f <= w7 when "1000" => f <= w8 when "1001" => f <= w9 when "1010" => f <= w10 when "1011" => f <= w11 when others => f <= 'z'; end case end process end Behavioral;

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question: Given the VHDL code for a 16-to-1 Multiplexer, please provide a Test Bench file.

VHDL Code for a 16-to-1 Multiplexer:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux16to1 is
    Port ( w0 : in STD_LOGIC;
           w1 : in STD_LOGIC;
           w2 : in STD_LOGIC;
           w3 : in STD_LOGIC;
           w4 : in STD_LOGIC;
           w5 : in STD_LOGIC;
           w6 : in STD_LOGIC;
           w7 : in STD_LOGIC;
           w8 : in STD_LOGIC;
           w9 : in STD_LOGIC;
           w10 : in STD_LOGIC;
           w11 : in STD_LOGIC;
           s : in STD_LOGIC_VECTOR(3 DOWNTO 0);
           f : out STD_LOGIC);
end mux16to1;

architecture Behavioral of mux16to1 is

begin
            process (s)

begin
            case s is
                        when "0000" => f <= w0
                        when "0001" => f <= w1
                        when "0010" => f <= w2
                        when "0011" => f <= w3
                        when "0100" => f <= w4
                        when "0101" => f <= w5
                        when "0110" => f <= w6
                        when "0111" => f <= w7
                        when "1000" => f <= w8
                        when "1001" => f <= w9
                        when "1010" => f <= w10
                        when "1011" => f <= w11
                        when others => f <= 'z';
            end case
end process

end Behavioral;

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