Question 4 1 pts locality means that an instruction or data item that has been recently accessed will likely be re- accessed soon in the future. O Associative O Temporal O Context O Spatial Question 5 1 pts Consider the typical memory hierarchy in modern computer systems. Which of the following components has the fastest access time in general? O Main memory O Registers O Cache O Solid-state disk Question 6 1 pts is a fault resulting from a reference to a non-memory-resident page of memory. O Disk fault O CPU fault O /0 fault O Page fault

Question 4 1 pts locality means that an instruction or data item that has been recently accessed will likely be re- accessed soon in the future. O Associative O Temporal O Context O Spatial Question 5 1 pts Consider the typical memory hierarchy in modern computer systems. Which of the following components has the fastest access time in general? O Main memory O Registers O Cache O Solid-state disk Question 6 1 pts is a fault resulting from a reference to a non-memory-resident page of memory. O Disk fault O CPU fault O /0 fault O Page fault

Name: Question 41 ptslocality means that an instruction or data item that h
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Question 41 ptslocality means that an instruction or data item that has been recently accessed will likely be re-accessed soon in the future.O AssociativeO TemporalO ContextO SpatialQuestion 51 ptsConsider the typical memory hierarchy in modern comp

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. Could you hand draw the page table, if possible a) Suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) b) What is the size of the two-level page table
Main memory size is 16 pages. Size of swap file on hard disk is 64 pages. Operating system locks down pages 0, 1, 2 and 7 in the main memory. Two programs are started and both are provided with a virtual address space of 10 pages. Initially operating system allocates 5 pages of main memory for each program and the rest from swap file. Virtual address space of each program starts from page 0. Construct page tables for both programs at program startup. A page table consists of P-bit which tells if the page is present in the main memory (1 = page is in main memory) and address of the page. Address tells either real address in main memory or the address of the page in swap file. b. A computer with a paged virtual memory system executes two load instructions that are adjacent to each other in memory. Describe the worst case scenario (in terms of performance) that can occur during the execution of the two instructions and explain under which conditions this case occurs. How does this affect…
Consider a virtual memory system with the following characteristics for accessing memory: 1 nanosecond for a read operation with a hit in cache 5 nanoseconds for a read operation with a miss in cache 2 nanoseconds for a write operation with a hit in cache 10 nanoseconds for a write operation with a miss in cache The cache hit ratio is 0.9 If a sequence of instructions were executed: 100 instruction fetch operations, 60 memory operand read operations, and 40 memory operand write operations, what would be the average memory access time (in nanoseconds) in executing the sequence of instructions:
A virtual memory has a page size of 16 words. There are 8 pages and 4 blocks. The associative memory page table contains the following entries. (Addresses are given HEX form): Page Block a) For the following virtual addresses find the CPU addresses: 3A, 5B, 1 3 b) For the following CPU addresses find the virtual addresses: 0C, 2D 1 4
In designing a computer’s cache system, the cache block or cache line size is an important parameter. Which of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller cache tag and hence lower cache tag overhead A smaller block size implies a larger cache tag and hence lower cache hit time A smaller bock size incurs a lower cache miss penalty
Suppose we have a byte-addressable computer with a cache that holds 8 blocks of 4 bytes each. Assuming that each memory address has 8 bits, to which cache block would the hexadecimal address 0x2D map if the computer uses direct mapping? Blocks are numbered starting at 0
4. Suppose a computer using a fully associative cache has 2^24 byte of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes. a) How big in kilobytes is main memory? b) How big in bytes is cache? In kilobytes? c) How many blocks of main memory are there? d) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? e) To which cache block will the memory address 0x01D8729A map?
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) To which cache block will the memory address 0x01D872 map?
5. A computer has an L1 and L2 cache, backed up by DRAM which is backed up by virtual memory. The TLB and L1 caches have hit times of .5 ns. The TLB's backup is the page table in DRAM while L1 cache's backup is an L2 cache. The L2 cache has a hit time of 1.5 ns. DRAM has a hit time of 10 ns. Swap space has a hit time of 2,500,000 ns. The hit rates are: TLB: 98.8%, L1: 91.5%, L2: 97.7%, DRAM: 99.9998% and swap space 100%. What is the effective access time?