Q2. [Consider a 48-bit virtual address space. The system uses a page size of 4KBand two-level hierarchical paging. Therefore, the page table is divided into 4KB pages and thelogical address has the following format:P1a) [Below are the relevant tables. The values are provided in hexadecimal.Outer Page TablePage A of Page Table0Page A of PT0FEE113BCX124C3D(rest are invalid)Page B of PT(rest are invalid)Size of P1 =00000000000023XWhat is the size (number of bits) of each of the following logical address fields:bits000003003102P2000001002777Size of P2 =Size of Offset=b)what is the physical/logical address corresponding to each of the followingshown logical/physical addresses. Answer "Bad logical address" if the logical address isinvalid.Logical AddressbitsOffsetbitsPage B of the Page Table0330144B2E55X(rest are invalid)Physical Address44B3BC

Q2. [ Consider a 48-bit virtual address space. The system uses a page size of 4KB and two-level hierarchical paging. Therefore, the page table is divided into 4KB pages and the logical address has the following format: P1 a) [ Below are the relevant tables. The values are provided in hexadecimal. Outer Page Table Page A of Page Table 0 Page A of PT 0 FEE 1 Page B of PT 1 3BC X (rest are invalid) Size of P1 = 000000000000 P2 2 3 X 000003003102 000001002777 What is the size (number of bits) of each of the following logical address fields: bits bits Offset 124 C3D (rest are invalid) Size of P2 = Size of Offset= b) In what is the physical/logical address corresponding to each of the following shown logical/physical addresses. Answer "Bad logical address" if the logical address is invalid. Logical Address bits Page B of the Page Table 0 330 1 44B 2 X Physical Address 44B3BC E55 (rest are invalid)

Q2. [ Consider a 48-bit virtual address space. The system uses a page size of 4KB and two-level hierarchical paging. Therefore, the page table is divided into 4KB pages and the logical address has the following format: P1 a) [ Below are the relevant tables. The values are provided in hexadecimal. Outer Page Table Page A of Page Table 0 Page A of PT 0 FEE 1 Page B of PT 1 3BC X (rest are invalid) Size of P1 = 000000000000 P2 2 3 X 000003003102 000001002777 What is the size (number of bits) of each of the following logical address fields: bits bits Offset 124 C3D (rest are invalid) Size of P2 = Size of Offset= b) In what is the physical/logical address corresponding to each of the following shown logical/physical addresses. Answer "Bad logical address" if the logical address is invalid. Logical Address bits Page B of the Page Table 0 330 1 44B 2 X Physical Address 44B3BC E55 (rest are invalid)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

10.5 Consider the page table for a system with 12-bit virtual and physical addresses and 256-byte pages. Page Page Frame 1 2 2 C 3 A 4 7 8 B 9 The list of free page frames is D, E, F (that is, D is at the head of the list, E is second, and Fis last). A dash for a page frame indicates that the page is not in memory. Which of the following virtual addresses results in page fault? Select all that apply A)111 B)OFF C)9EF D)700|
Q e
Part 1: Preliminary Summarize the difference between binary machine language, assembly language, and high-level source files like C. Contrast the difference between a compiler, assembler, and linker What is the difference between the data segment and the text segment of in an assembly language program? What register is used as the stack pointer? What is a ebreak instruction in the sample program? How would you define a constant named 'BLUE' and assign it to the value OX00F in assembly language? Describe how to implement the psuedo-instruction li t1, e using a native instruction.
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
4. Suppose we want to create a stack of names that vary in length. Why is it advantageous to store the names in separate areas of memory and then build the stack out of pointers to these names rather than allowing the stack to contain the names themselves?
Suppose a malloc implementation returns 8-byte aligned addresses and uses an explicit free list where the next and previous pointers are each 32-bits. Blocks have a 32-bit header and 32-bit footer, where the low-order bit of the header and footer are used to indicate whether the block is allocated (1) or free (0). Furthermore, the block size (which includes the header, payload, footer, and any necessary padding) is rounded up to the nearest multiple of 8, and this size (in bytes) is stored in the header and footer. Assume any padding must be between the payload and the footer.If we call malloc(1), what block size will be allocated, in bytes? With the same conditions as #1, and assuming we've already called malloc(1), if the heap used by malloc starts at address 0x4000 (16384 in decimal), what address would be returned if we then called malloc(32)?
What would be some advantages of having a larger page size of 16 KiB? What are some disadvantages?
Programming Language Pragmatics, 4th Edition
Consider a file system that uses indexed allocation with a maximum of one index node per file. Suppose the index node occupies 4096 bytes, that each block pointer occupies 4 bytes. Ignore the metadata associated with the file that is usually contained in the index node. How large should a block be (in bytes) so that this scheme is able to completely access files on a 1 GB file system?
Consider a 1GByte memory that can be managed by either a bitmap or a linked list. The memory allocation unit is in units of n bytes, which is some power of 2. Memory in the linked list is either marked as free or used (i.e. holes and segments). Assume that each node in the list requires 64 total bits (including a memory address, a length, and a pointer to the next linked list element). Also, make the (unrealistic) assumption that holes and segments are all 32KB (215 bytes) and that they alternate so that there is no coalescing of adjacent holes. It also means that each linked list element covers either a 32KB hole or a 32KB segment. Determine how much memory each data structure uses (the bitmap will be in terms of n)
Discuss the concepts of merging arrays and pointers in the structure type design, definition. There are ip_adresses, protocols are stored in a file named as internet.txt file. You are asked to design a pipeline statement that can printout a particular segment of the ip adresses in the deceasing order. Explain the system commands, pipeline symbols that you will use to design the complete statement.
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.