Please describe what this testbench code is doing. You can use comments for each line if that is easier for you. This code is using Verilog.
Please describe what this testbench code is doing. You can use comments for each line if that is easier for you. This code is using Verilog.
`timescale 1ns / 1ps
module testbench01();
reg btn_clk, Xa, Xb, Xc, Xd, Xe, Xf, load, reset, s;
reg [4:0]S;
wire Ya, Yb, Yc, Yd, Ye, Yf;
wire loadLED, resetLED, sLED;
wire [4:0]P;
reg [3:0]an;
reg [0:7]seg;
integer i, j;
Project_tester uut(
.btn_clk(btn_clk),
.Xa(Xa),
.Xb(Xb),
.Xc(Xc),
.Xd(Xd),
.Xe(Xe),
.Xf(Xf),
.load(load),
.reset(reset),
.s(s),
.Ya(Ya),
.Yb(Yb),
.Yc(Yc),
.Yd(Yd),
.Ye(Ye),
.Yf(Yf),
.loadLED(loadLED),
.resetLED(resetLED),
.sLED(sLED),
.P(P));
initial
begin
$display("\nstart\n");
btn_clk = 0; Xa = 0; Xb = 0; Xe = 0; Xf = 0; load = 1; reset = 0; s = 0;
#100;
for (i = 0; i < 12; i = i + 1)
begin
load = 1;
s = i;
#3 btn_clk = !btn_clk;
#3 btn_clk = !btn_clk;
$display("%b",P);
Xd = 1;
#3 btn_clk = !btn_clk;
#3 btn_clk = !btn_clk;
$display("%b",P);
end
$display("ended\n");
$finish;
end
endmodule
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