Our system is using virtual memory and has 48-bit virtual address space and 32-bit physical address space. Page size is 8 KiB. (a) How many entries are needed for a single-level page table? What does the two-level page table look like if the part of the virtual address which identifies the page number is split into two fields, such that the second part has 3 bits more than the first part? (b) Our system also has the TLB (Translation Lookaside Buffer) with 64 entries. We run the following program which reads 32-bit integers from an array of size 200 000: int[] t = new int [200000]; for (int i=19; i>=0; i--) { } for (int j=0; j<10000; j++) { // we access t[ i + 20 * j ] } How efficient is the TLB in this case? More precisely, how many times will a TLB miss occur (resulting in page table lookup)? Assume that the TLB is initially empty.

Our system is using virtual memory and has 48-bit virtual address space and 32-bit physical address space. Page size is 8 KiB. (a) How many entries are needed for a single-level page table? What does the two-level page table look like if the part of the virtual address which identifies the page number is split into two fields, such that the second part has 3 bits more than the first part? (b) Our system also has the TLB (Translation Lookaside Buffer) with 64 entries. We run the following program which reads 32-bit integers from an array of size 200 000: int[] t = new int [200000]; for (int i=19; i>=0; i--) { } for (int j=0; j<10000; j++) { // we access t[ i + 20 * j ] } How efficient is the TLB in this case? More precisely, how many times will a TLB miss occur (resulting in page table lookup)? Assume that the TLB is initially empty.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 16 bytes: (a) Determine the size of the offset field. (b) Determine the size of the tag field.
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?
Suppose that a machine has 38-bit virtual addresses and 32-bit physical addresses.(a) What is the main advantage of a multilevel page table over a single-level one?(b) With a two-level page table, 16-KB pages, and 4-byte entries, how many bits should be allocated for the top-level page table field and how many for the next-level page table field? Explain.
Suppose a computer using fully associative cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?
Our system is using virtual memory and has 48-bit virtual address space and 32-bit physical address space. Page size is 16 KiB. (a) How many entries are needed for a single-level page table? What does the two-level page table look like if the part of the virtual address which identifies the page number is split into two fields of equal size? (b) Our system also has the TLB (Translation Lookaside Buffer) with 128 entries. We run the following program which reads 32-bit integers from an array of size 200 000: int[] t = new int [200000]; for (int i=399; i>=0; i--) { for (int j=0; j<500; j++) { } } // we access t[ i +400 * j ] How efficient is the TLB in this case? More precisely, how many times will a TLB miss occur (resulting in page table lookup)? Assume that the TLB is initially empty.
If we had a computer that can only address data in bytes, but it has fully associative mapping, 16-bit main memory addresses, and 32-bit cache memory blocks. If each block is 16 bytes in size, then...(a) Count the number of bytes in the offset field.The tag field's size in pixels must be calculated (b).
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? With this system, what’s the maximum number of pages that a process can have? Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number.
In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.
Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. Supposed also that each block contains 16 bytes. The size of the offset field is 19 bits and the size of the block field is 0.625 bytes.
Consider a memory system that generates 16-bits addresses and the frame size is 32-byte. At time To the status of the page table is given below. Page Table Entry Page # 1911 11 561 56 644 1068 1884 52 58 42 194 46 a) What is the maximum number of entries within a single page/frame? b) What is the maximum number of page table entries in the memory system? c) Using the given page table, determine the physical addresses for the following logical addresses. Write down the physical addresses in binary and decimal format. (i) (iii) 0101000010001011 1110101110010111 (ii) (iv) 0001100001100111 1110111011101001