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(d) Assuming that the memory access takes 100 cycles to access DRAM, the system has 4-level page table (i.e., a page walk have to access the memory 4 times before it can access its data), an TLB access takes 1 cycle, and a L1 cache access to the set takes 1 cycle and the tag comparison in the L1 cache takes another 1 cycle. How long does it takes to load a data that has a TLB miss and a L1 cache hit? Feels free to explain your answer.

(d) Assuming that the memory access takes 100 cycles to access DRAM, the system has 4-level page table (i.e., a page walk have to access the memory 4 times before it can access its data), an TLB access takes 1 cycle, and a L1 cache access to the set takes 1 cycle and the tag comparison in the L1 cache takes another 1 cycle. How long does it takes to load a data that has a TLB miss and a L1 cache hit? Feels free to explain your answer.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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(c) What is the physical address for a virtual address 0x0000beef if this system were to use a single level 64KB page instead? Put in Not enough information if the table does not provide enough information to get the physical address. (d) Assuming that the memory access takes 100 cycles to access DRAM, the system has 4-level page table (i.e., a page walk have to access the memory 4 times before it can access its data), an TLB access takes 1 cycle, and a L1 cache access to the set takes 1 cycle and the tag comparison in the L1 cache takes another 1 cycle. How long does it takes to load a data that has a TLB miss and a L1 cache hit? Feels free to explain your answer. Initials: (e) Now let's run this on a virtual machine (VM). Assuming that the memory access takes 100 cycles to access DRAM, the system has 4-level page table (i.e., a page walk have to access the memory 4 times before it can access its data), assume we have a TLB-miss and a L1 cache hit. With a virtual machine, each physical address on your VM's Operating System is actually a virtual address on the host machine. What is the number of cycles it would take to translate a virtual address inside a VM on your host machine. Feels free to explain your answer. Initials: Log Table N 1 2 4 8 11/15 16 32 64 128 256 512 1024 (1k) 2048 (2k) 4096 (4K) 8192 (8k) 16384 (16k) 32768 (32k) 62236 (64k) 131072 (128k) 262144 (256k) 524288 (512k) 1048576 (1M) 2097152 (2M) 4194304 (4M) 8388608 (8M) 16777216 (16M) 12/15 log₂ N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Transcribed Image Text:(c) What is the physical address for a virtual address 0x0000beef if this system were to use a single level 64KB page instead? Put in Not enough information if the table does not provide enough information to get the physical address. (d) Assuming that the memory access takes 100 cycles to access DRAM, the system has 4-level page table (i.e., a page walk have to access the memory 4 times before it can access its data), an TLB access takes 1 cycle, and a L1 cache access to the set takes 1 cycle and the tag comparison in the L1 cache takes another 1 cycle. How long does it takes to load a data that has a TLB miss and a L1 cache hit? Feels free to explain your answer. Initials: (e) Now let's run this on a virtual machine (VM). Assuming that the memory access takes 100 cycles to access DRAM, the system has 4-level page table (i.e., a page walk have to access the memory 4 times before it can access its data), assume we have a TLB-miss and a L1 cache hit. With a virtual machine, each physical address on your VM's Operating System is actually a virtual address on the host machine. What is the number of cycles it would take to translate a virtual address inside a VM on your host machine. Feels free to explain your answer. Initials: Log Table N 1 2 4 8 11/15 16 32 64 128 256 512 1024 (1k) 2048 (2k) 4096 (4K) 8192 (8k) 16384 (16k) 32768 (32k) 62236 (64k) 131072 (128k) 262144 (256k) 524288 (512k) 1048576 (1M) 2097152 (2M) 4194304 (4M) 8388608 (8M) 16777216 (16M) 12/15 log₂ N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
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