Find the Structual hazards that may occur when pipelining the following commands in a MIPS processor with 5 steps (IF, ID, EX, MEM, WB) for Pipeline and a separate ALU for each of the Add / Sub, Mul, Div operations. ( Consider that FP_Add = 3 cycles, FP_Multiply = 2 cycles, FP_Divide = 1 cycle.)  Inst-1: FP_Add(F1,F3,F5) Inst-2: FP_Multiply(F5,F1,F2) Inst-3: FP_Divide(F1,F4,F3) answers  a)inst-1&inst-2  and  &inst-3 b)inst-2&inst-3 only c)inst-1&inst-3 only d)inst-2&inst-3  and inst-1&inst-2 e)inst-1&inst-2 only

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