EXAMPLE 7.6 For the n-channel depletion-type MOSFET of Fig. 7.30, determine: a. Ipo and VGS b. VDs. V₁0- H C₁ R₁ R₂ www 110 ΜΩ G • 10 ΜΩ Rp 9 18 V Rs JE 1,8 ΚΩ D ENGG CC PPT Notes 01Sep2020 V01 C₂ 750 92 H DSS = 6 mA Vp = -3 V -。V FIG. 7.30 Figure 2.8 Example of a D-MOSFET Voltage Divider Circuit. EEETE 3102N Electronics II

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Publisher:Robert L. Boylestad
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2.8 D-MOSFET Voltage Divider Bias Configuration
EXAMPLE 7.6 For the n-channel depletion-type MOSFET of Fig. 7.30, determine:
a. Ipo and VGS,
b. Vps.
V₁0-
H
C₁
R₁
R₂
www
110 ΜΩ
G
10 ΜΩ
RD
Rs
9 18 V
E
ENGG CC PPT Notes 01Sep2020_V01
1.8 ΚΩ
D
S
C₂
HH
DSS = 6 mA
Vp = -3 V
750 92
V₂
FIG. 7.30
Figure 2.8 Example of a D-MOSFET Voltage Divider Circuit.
EEETE 3102N: Electronics II
Transcribed Image Text:2.8 D-MOSFET Voltage Divider Bias Configuration EXAMPLE 7.6 For the n-channel depletion-type MOSFET of Fig. 7.30, determine: a. Ipo and VGS, b. Vps. V₁0- H C₁ R₁ R₂ www 110 ΜΩ G 10 ΜΩ RD Rs 9 18 V E ENGG CC PPT Notes 01Sep2020_V01 1.8 ΚΩ D S C₂ HH DSS = 6 mA Vp = -3 V 750 92 V₂ FIG. 7.30 Figure 2.8 Example of a D-MOSFET Voltage Divider Circuit. EEETE 3102N: Electronics II
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