Data Path Cycles: Use the following data to answer the questions below: Memory Access: 540 ps ALU and adders: 300 ps Register File: 200 ps Assume that mux, control unit, PC accesses, sign extension unit and wires have no latency. A: 1. Using the datapath diagram (displayed), determine the time that each of the types of instructions would require. R ____________ Load _________ Store _________ BEQ _________ JUMP________ 2. If every instruction executes in 1 clock cycle of a fixed length, what is the length of one clock cycle? 2. ____________ 3. If every instruction executes in 1 clock cycle using a variable length clock, with an instruction mix of 15% loads, 25% stores, 45% ALU type, 11% branches and 4% jumps, what is the average length clock cycle? 3. ____________ 4. In order to implement a pipelined design for the datapath, what would be the length of a cycle (in ps)? 4. ____________ 5. What is the average time required for each instruction to pass through the pipeline as displayed? 5. ____________ 6. Using a pipelined design and the above mix of instructions, where a jump always causes a 1 cycle delay, 20% of the load instructions are immediately followed by an instruction that uses the result (causing a 1-cyle delay), and 15% of the branch instructions are mis-directed (causing a 2-cycle delay), what is the average effective number of cycles once the pipeline is loaded? 6. ____________
Data Path Cycles:
Use the following data to answer the questions below:
Memory Access: 540 ps
ALU and adders: 300 ps
Register File: 200 ps
Assume that mux, control unit, PC accesses, sign extension unit and wires have no latency.
A:
|
1. Using the datapath diagram (displayed), determine the time that each of the types of instructions would require. |
R ____________ |
|
2. If every instruction executes in 1 clock cycle of a fixed length, what is the length of one clock cycle? |
2. ____________ |
|
3. If every instruction executes in 1 clock cycle using a variable length clock, with an instruction mix of 15% loads, 25% stores, 45% ALU type, 11% branches and 4% jumps, what is the average length clock cycle? |
3. ____________ |
|
4. In order to implement a pipelined design for the datapath, what would be the length of a cycle (in ps)?
|
4. ____________ |
|
5. What is the average time required for each instruction to pass through the pipeline as displayed? |
5. ____________ |
|
6. Using a pipelined design and the above mix of instructions, where a jump always causes a 1 cycle delay, 20% of the load instructions are immediately followed by an instruction that uses the result (causing a 1-cyle delay), and 15% of the branch instructions are mis-directed (causing a 2-cycle delay), what is the average effective number of cycles once the pipeline is loaded? |
6. ____________ |
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