Consider the two designs D1 and D2 for a pipeline processor. D1 has 5 pipeline stages with execution time of 4 ns, 3 ns, 5ns, 3ns and 4 ns. While the design D2 has 8 pipeline stages each with 4ns execution time. The buffer delay for both designs is 1 ns. How much time can be reduced in using design D2 over design D1 for executing 100 instructions?

Consider the two designs D1 and D2 for a pipeline processor. D1 has 5 pipeline stages with execution time of 4 ns, 3 ns, 5ns, 3ns and 4 ns. While the design D2 has 8 pipeline stages each with 4ns execution time. The buffer delay for both designs is 1 ns. How much time can be reduced in using design D2 over design D1 for executing 100 instructions?

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Question

Consider the two designs D1 and D2 for a pipeline processor. D1 has 5
pipeline stages with execution time of 4 ns, 3 ns, 5ns, 3ns and 4 ns. While
the design D2 has 8 pipeline stages each with 4ns execution time. The
buffer delay for both designs is 1 ns. How much time can be reduced in
using design D2 over design D1 for executing 100 instructions?

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