0.1 ns. b) [15] If there is a stall every four instructions, what is the CPI of the new machine? c) [10] What is the speedup of the pipelined machine over the single-cycle machine? d) [10] If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?
We begin with a computer implemented in single-cycle implementation. When the
stages are split by functionality, the stages do not require exactly the same amount of time. The original
machine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID,
1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns.
b) [15]<C.2> If there is a stall every four instructions, what is the CPI of the new machine?
c) [10]<C.2> What is the speedup of the pipelined machine over the single-cycle machine?
d) [10]<C.2> If the pipelined machine had an infinite number of stages, what would its speedup be over
the single-cycle machine?
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