Consider the following two SimpleRISC code snippets. Data hazards have to be handled in hardware. Let us consider two processors A and B: A supports only data interlocks, while B supports data interlocks and value forwarding. In each processor, in which cycle will the final instruction pass through the RW stage? Give the pipeline diagram in each case. (Assume the first instruction is in IF stage in cycle 1 in each case). (i) [1] st r3, 24[r1] [2] ld r4, 24[r1] (ii) [1] add r1, r1, r2 [2] sub r3, r1, r4 [3] add r4, r5, r6

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