b. Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline consisting of fetch, decode and execute stages. Show how the instructions in the following ARM code would pass throught the pipeline by copying and completing the table below for the first nine cycles only. The first three lines have been completed for you. You should list if and where any structural hazards and/or any control hazards would occur. MOV R1,#42 LDRB R3, [RO,R1] EOR R3, R3, R2 STRB R3, [RO,R1] SUB R1, R1,#1 CMP R1, #0 crypt BGE сrypt MOV RO, #0 MOV PC,R14 Cycle Fetch Decode Execute MOV R1,#42 2 LDRB R3, (RO, R1] MOV R1,#42 3 EOR R3,R3, R2 LDRB R3, [RO,R1] MOV R1,#42 4 7 8
b. Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline consisting of fetch, decode and execute stages. Show how the instructions in the following ARM code would pass throught the pipeline by copying and completing the table below for the first nine cycles only. The first three lines have been completed for you. You should list if and where any structural hazards and/or any control hazards would occur. MOV R1,#42 LDRB R3, [RO,R1] EOR R3, R3, R2 STRB R3, [RO,R1] SUB R1, R1,#1 CMP R1, #0 crypt BGE сrypt MOV RO, #0 MOV PC,R14 Cycle Fetch Decode Execute MOV R1,#42 2 LDRB R3, (RO, R1] MOV R1,#42 3 EOR R3,R3, R2 LDRB R3, [RO,R1] MOV R1,#42 4 7 8
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![b. Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline
consisting of fetch, decode and execute stages.
Show how the instructions in the following ARM code would pass throught the pipeline
by copying and completing the table below for the first nine cycles only. The first three
lines have been completed for you. You should list if and where any structural hazards
and/or any control hazards would occur.
MOV R1, #42
LDRB R3, [RO, R1]
EOR R3,R3, R2
STRB R3, [RO, R1]
SUB R1,R1#1
crypt
CMP R1, #0
BGE crypt
MOV RO, #0
MOV PC, R14
Cycle
Fetch
Decode
Execute
1
MOV R1,#42
2
LDRB R3, [RO, R1]
MOV R1,#42
3
EOR R3,R3, R2
LDRB R3, [RO, R1]
MOV R1,#42
4
6.
8](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F7664b6c7-b372-431d-82e6-04f456134eee%2F1007737f-e2ff-4d93-8c83-7610a170cf7b%2F27n91l_processed.png&w=3840&q=75)
Transcribed Image Text:b. Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline
consisting of fetch, decode and execute stages.
Show how the instructions in the following ARM code would pass throught the pipeline
by copying and completing the table below for the first nine cycles only. The first three
lines have been completed for you. You should list if and where any structural hazards
and/or any control hazards would occur.
MOV R1, #42
LDRB R3, [RO, R1]
EOR R3,R3, R2
STRB R3, [RO, R1]
SUB R1,R1#1
crypt
CMP R1, #0
BGE crypt
MOV RO, #0
MOV PC, R14
Cycle
Fetch
Decode
Execute
1
MOV R1,#42
2
LDRB R3, [RO, R1]
MOV R1,#42
3
EOR R3,R3, R2
LDRB R3, [RO, R1]
MOV R1,#42
4
6.
8
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