Assume the following performance characteristics on a cache read miss: one clock cycle to access cache memory, one clock cycle to access main memory, and six clock cycles to transfer a 32-bit word to the processor and cache.  If the cache line size is one word, the miss penalty will be 1+1+6 = 8.0. Given this information: A. What is the miss penalty if the cache line size is four words and a multiple, nonburst transfer is executed?  B. What is the miss penalty if the cache line size is four words and a transfer is executed, with one clock cycle per word transfer?

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A: please see the next step for solution