(a) The n-well in a CMOS process covers an area of 1 cm× 0.5 cm, and the junction saturation current density is 500 pA/cm2. What is the total leakage current of the reverse-biased well? (b) Suppose the drain and source regions of the NMOS and PMOS transistors are 2µm × 5µm, and the saturationcurrent density of the junctions is 100 pA/cm2. If the chip has 20 million inverters, what is the total leakage current due to the reverse-biased junctions when vO =2.5 V? Assume VDD =2.5 V and VSS =0 V. (c) When vO =0 V?
(a) The n-well in a CMOS process covers an area of 1 cm× 0.5 cm, and the junction saturation current density is 500 pA/cm2. What is the total leakage current of the reverse-biased well? (b) Suppose the drain and source regions of the NMOS and PMOS transistors are 2µm × 5µm, and the saturationcurrent density of the junctions is 100 pA/cm2. If the chip has 20 million inverters, what is the total leakage current due to the reverse-biased junctions when vO =2.5 V? Assume VDD =2.5 V and VSS =0 V. (c) When vO =0 V?
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(a) The n-well in a CMOS process covers an area of 1 cm× 0.5 cm, and the junction saturation current density is 500 pA/cm2. What is the total leakage current of the reverse-biased well? (b) Suppose the drain and source regions of the NMOS and PMOS transistors are 2µm × 5µm, and the saturation
current density of the junctions is 100 pA/cm2. If the chip has 20 million inverters, what is the total leakage current due to the reverse-biased junctions when vO =2.5 V? Assume VDD =2.5 V and VSS =0 V. (c) When vO =0 V?
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