a) Assume that a direct mapped cache memory stores 1024 blocks and 64 bytes per block. i) What is storage capacity of the cache memory in bytes? ii) What is length of tag bits if 20 bits addressing is used in CPU? b) Draw a table indicating the initial state (Valid, Tag bits and Data) of a direct mapped cache with 8-blocks and 1 word per block. (Assume that words have 5-bits address length). Then, fill / modify the table (valid, tag and data columns) by accessing word-addresses below in given order. (e.g. old value → new value → ...) 5, 10, 26, 5, 10, 23, 20, 5, 23, 10 (Show memory accesses by writing Mem[Word Address] in “Data” column) c) Which accesses are “hit” and which accesses are “miss” in question (b)? 5, 10, 26, 5, 10, 23, 20, 5, 23, 10
a) Assume that a direct mapped cache memory stores 1024 blocks and 64 bytes per block. i) What is storage capacity of the cache memory in bytes? ii) What is length of tag bits if 20 bits addressing is used in CPU? b) Draw a table indicating the initial state (Valid, Tag bits and Data) of a direct mapped cache with 8-blocks and 1 word per block. (Assume that words have 5-bits address length). Then, fill / modify the table (valid, tag and data columns) by accessing word-addresses below in given order. (e.g. old value → new value → ...) 5, 10, 26, 5, 10, 23, 20, 5, 23, 10 (Show memory accesses by writing Mem[Word Address] in “Data” column) c) Which accesses are “hit” and which accesses are “miss” in question (b)? 5, 10, 26, 5, 10, 23, 20, 5, 23, 10
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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a) Assume that a direct mapped cache memory stores 1024 blocks and 64 bytes per block.
i) What is storage capacity of the cache memory in bytes?
ii) What is length of tag bits if 20 bits addressing is used in CPU?
b) Draw a table indicating the initial state (Valid, Tag bits and Data) of a direct mapped cache with 8-blocks and 1 word per block. (Assume that words have 5-bits address length). Then, fill / modify the table (valid, tag and data columns) by accessing word-addresses below in given order. (e.g. old value → new value → ...)
5, 10, 26, 5, 10, 23, 20, 5, 23, 10
(Show memory accesses by writing Mem[Word Address] in “Data” column)
c) Which accesses are “hit” and which accesses are “miss” in question (b)?
5, 10, 26, 5, 10, 23, 20, 5, 23, 10
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