+VDDRpRsR₁Fig. 4 6. A CG amplifier using an NMOS transistor for which g-4mA/V has a 5-kQ drain resistance RD and a 5-k2 load resistance R₁. The amplifier is driven by a voltage source having a 500 2 resistance. What is theinput resistance of the amplifier? What is the overall voltage gain G₁? By that factor must the bias currentID of the MOSFET be changed so that Rin matched Raig? (Fig. 4)

Step 1: Step 2: Step 3: Step 4:

Answered: +VDD Rp Rs R₁ Fig. 4 6. A CG amplifier…

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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a) Draw the circuit diagram of a basic current mirror circuit. Define gain and error of a current mirror. What are the sources of error in a current mirror? b) Derive the expression for the output resistance Ro and determine the % error due to the output resistance for Wilson current mirror shown in Ckt. 3 (derivation not required for %error). Mention two merits of this circuit over cascode current mirror. c) Find the currents IIN and IOUT in the current mirror circuit shown in Ckt. 4. Assume that all the transistors are matched, base to emitter voltage VBE = 0.7 V, R = 26 kΩ, and ? and ro to be infinite. d) If ?=260, find the percentage of error due to finite ? for Ckt. 4. How the error can be minimized? Draw the modified circuit and write the corresponding error expression for the modified circuit
Consider the circuit shown below of a common source amplifier with a current mirror bias. Find the following: a. Find kp and kn. b. Find the drain current of M2 given that lBIas = 2mA and Vout = 2.5V. c. Find the gm and ro of transistor M1. d. Sketch the small signal model of transistor M3 (Hint: Is there any small signal in any terminal of M3? If yes, then where is it? If no, then what happens to the small signal model?). It is given that the NMOS (M1) parameters are H.Cox = 3mA/V² , VrH,n = 0.5V and A = 0.02 and the PMOS (M2 and M3) parameters are H,Cox = 1mA/V² and VrH,p = -0.6V . The PMOS transistor M3 does not have channel length modulation while PMOS transistor M2 has 1 = 0.02. It is also given that the dimensions of M2 and M3 have equal widths of 5µm and lengths of L2 = 3µm and L3 = 1.5µm, respectively. M1 has length of L1 = 1µm and width of W1 = 2µm. %3D 5V 5V M3 M2 VOUT IBIAS M, - VIN
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The p-channel MOSFET in the circuit below has V = 1 V and k, = 2 mA/V² (A = 0). + 5 V 9 mA (. vout Q1 10 k VS -5 v a) Is this amplifier a common-source, common-drain, or common-gate configuration? b) Determine the d.c. biasing by calculating VsG and Vsp. c) What is the amplificr's gain A and output resistance Rout?
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