4.0 You are building a computer with a hierarchical memory system that consists of separate instruction and data caches followed by main memory. You are using a MIPS single cycle processor running at 2.5 GHz. 4.0.1 Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5.5 % miss rate. On a cvache miss, the processor stalls for 40 ns to access main memory, then resumes normal operation. Taking cache misses into account, what is the average memory access time? 4.0.2 Consider a benchmark application that has 20% loads, 15% stores, 10% branches, and 55% data processing instructions. Taking the non-ideal memory system into account, what is the average CPI for this benchmark? 4.0.3 Now suppose the instruction cache is also non-ideal and has a 2.5% miss rate. What is the average CPI for the benchmark in 4.0.2? Take into account both instruction and data cache misses.
4.0 You are building a computer with a hierarchical memory system that consists of separate instruction and data caches followed by main memory. You are using a MIPS single cycle processor running at 2.5 GHz.
4.0.1 Suppose the instruction cache is perfect (i.e., always hits) but the data cache has a 5.5 % miss rate. On a cvache miss, the processor stalls for 40 ns to access main memory, then resumes normal operation. Taking cache misses into account, what is the average memory access time?
4.0.2 Consider a benchmark application that has 20% loads, 15% stores, 10% branches, and 55% data processing instructions. Taking the non-ideal memory system into account, what is the average CPI for this benchmark?
4.0.3 Now suppose the instruction cache is also non-ideal and has a 2.5% miss rate. What is the average CPI for the benchmark in 4.0.2? Take into account both instruction and data cache misses.
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