3. Explain in paragraph format what is happening in this example:PCAddress>AddInstructionmemoryIF/IDInstruction1.1 LReadregister 1Readregister 2Registers Readdata 2WriteregisterWritedataReaddata16Sign-extend32ID/EXShiftleft 2(OMX_Add AddresultZeroALU ALUresultEX/MEMAddressWritedataDatamemoryReaddataMEM/WB

Name: 3. Explain in paragraph format what is happening in this example:PCAd
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Description: 3. Explain in paragraph format what is happening in this example:PCAddress>AddInstructionmemoryIF/IDInstruction1.1 LReadregister 1Readregister 2Registers Readdata 2WriteregisterWritedataReaddata16Sign-extend32ID/EXShiftleft 2(OMX_Add AddresultZeroAL

Introduction to Pipelining Pipelining is a method of breaking down a sequential process into…

Engineering

Computer Science

3. Explain in paragraph format what is happening in this example: Address >Add Instruction memory IF/D Read register 1 Read register 2 Write register Write data Read data 1 Registers Read data 2 16 Sign- extend ID/EX Shift left 2 Add result Add ALU Zero ALU result EX/MEM Address Write data Data memory Read data MEM/WB

3. Explain in paragraph format what is happening in this example: Address >Add Instruction memory IF/D Read register 1 Read register 2 Write register Write data Read data 1 Registers Read data 2 16 Sign- extend ID/EX Shift left 2 Add result Add ALU Zero ALU result EX/MEM Address Write data Data memory Read data MEM/WB

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=500 W=650 T1=100 T2=200 T3=300
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Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 6 bits, memory addresses are 64 bits, data size is 32 bits and register addresses are 5 bits. a. For each instruction set architecture shown in Figure A.1, how many addresses or names (including both memory and register), appear in each instruction for the code to compute C = A+ B, and what is the total code size? passor TOS Memory (A) Accumulator (C) Registry (D) Re loed oore Figure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the oper and is an input or the result of the orithmetic-logical unit ALU operation, or both an input and result Lighter shoes indicate inputs, and the dark shode indicates the result in a top of stack (TOS) register points to the top input operand, which is combined with the operand below. The first operand is removed from the stack, the result takes the place of the…
4. Write an instruction sequence that generates a byte-size integer in the memory location defined as RESULT. The value of the integer is to be calculated from the logic equation (RESULT) = (AL) · (NUM1) + (NUM2) · (AL) + (BL) Assume that all parameters are byte sized. NUM1, NUM2, and RESULT are the offset addresses of memory locations in the current data segment.
The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=800 T1=200 T2=200 T3=300
Add Add Sum 1 Shift left 1 Branch MemRead Instruction [6-0] MemtoReg ALUOP Control MemWrite ALUSCC RegWrite L3 Instruction [19-15] Read address Read register 1 PC Instruction (24-20] Read data 1 Instruction [31-0] Read register 2 Zero ALU ALU Read Instruction [11-7) Read data 2 Address Write result data Instruction register memory Write data Registers Write Data data memoryl Instruction (31-0) 32 Imm 64 ALU Gen control Instruction [30,14-12] During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory): x8=72. x18=56, DM(64) =48 During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address: all values are shown in decimal): 51868 Id x8.8(x18) Write below the value of the bus L1 in decimal: L1 Write below the value of the bus L2 in decimal: L2 Write below the value of the bus L3 in decimal: L3
In 6809, a portion of the memory has been randomly selected and shown here: ... C7 52 EC 89 FF 00 DC This portion of the memory may contain binary information related to one instruction. The instruction is: LDB #$52 LDD $FF,X None of the other options LDB $52 LDD $FF00,X
The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=600 W=770 T1=200 T2=200 T3=300