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- 1)Encode the binary data 1010101010 into an even parity Hamming code. 2)A direct mapped cache consists of 256 slots. Main memory contains 64K blocks of 16 words each. Access time of the cache is 15 ns, and that for the main memory is 120 ns. Assume that main memory is accessed in parallel with cache look up. Initially, the cache is empty. (a) Give the format of the memory address. (b) Compute the effective access time, if suppose the hit ratio for read is 90%.A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?Question 6 The IEEE Standard 754 representation of a floating point number is given as: 01101110110011010100000000000000. Determine the binary value represented by this number. a) A cache system is to be designed to store data from a 1 GB memory space. If each block of main memory contains 16 words, determine the number of blocks that are needed and draw the logical organization of the full address identifying the block ID portion and the word (offset) portion. b) c) Discuss the advantages of using glass substrate over aluminum substrate in the construction of the hard drive.
- QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)2. A byte-addressable computer uses 32-bit address to access main memory. Suppose the data cache contains 128 blocks and works in4-way set-associative. Each block size is 64B with one "valid" bit. a. How many bits in Tag, Index and Offset? b. Calculate the total cache size (in bits).6. For a direct mapped cache comprising 16 single word blocks answer the following questions. Assume address and word sizes are both 32 bits and that the memory is byte addressed (4 bytes per 32-bit word). Enter answers as numbers only. How many index bits are there? How many offset bits are there? How many tag bits are there?
- Computer Science Consider a direct-mapped cache with 8 lines, each holding 16 bytes of data. The cache is byte-addressable and the main memory consists of 64 KB, which is also byte-addressable. Assume that a program reads 16KB of memory sequentially. Answer the following questions:a) How many bits are required for the tag, index, and offset fields of a cache address?b) What is the cache size in bytes?c) What is the block size in bytes?d) What is the total number of blocks in main memory?e) How many cache hits and misses will occur for the program, assuming that the cache is initially empty?f) What is the hit ratio?g) Give an example virtual address (in BINARY) that will be placed in cache line 5.5. suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by the cache ; that is, what are the size of the tag and offset field. c) To which cache block will the memory address 0x01D872 map?A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?
- ) Assume a 32-bit memory address, and a 128KB direct-mapped cache with 64-byte blocks. Show how the memory address is divided into tag, index and offset. Indicate clearly how many bits are in each. 1b) Consider the memory address 0x2c0868. For the cache in part a, what are its tag and index? Show in binary. 1c) Suppose an access to 0x2c0868 is a cache miss. For the cache in part a, what are the addresses of the (aligned) words that are brought into the cache?CO. A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index ticlds respectively in the addresses generated by the processor?Question 2: Consider a memory of 64 Kbytes. It has a 2 Kbytes cache organized in a direct-mapped manner with 64 bytes per cache block. Assume that the size of each memory word is 1 byte. a) What is the length of the address provided by the processor? b) What is the number of blocks in main memory? c) How many lines does the cache have? d) Calculate the number of bits in each of the Tag, Block(SET), and Word fields (OFFSET) of the memory address.