EECS140_Lab 8

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University of Kansas *

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140

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Mechanical Engineering

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Jan 9, 2024

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Lab 8:EECS 140 ALU1 Arithmetic Logic Unit Objectives The objective of this laboratory is to apply knowledge of combinational logic designs to real world application by implementing an arithmetic logic unit into a field programmable gate array chip which can do addition, AND, OR and XOR operations. Discussion Figure 1: Flow chart for ALU

Figure 2: Internal Signals for ALU Click here to view the ALU block diagram (higher quality) The concept is to design and implement an arithmetic logic unit, which will have the ability to take two four bit binary numbers and depending on a two bit selector either add, logic AND, logic OR, or logic XOR the two inputs for a five bit binary output. You will use two seven-segment displays to display the binary output in hexadecimal format. Your inputs will range from the hexadecimal numbers 0 to F. Likewise, your outputs will range from 0 to 1E. In this lab you would be inserting the ripple carry adder design from your previous lab and the 7- segment display unit to display hexadecimal numbers. The code for the other components of the ALU is given to you below. Make sure you design your ALU component (toplevel) with the inputs and outputs of your existing components (adder, display, etc) in mind. Files Download and Add these source files to your new project in xilinx ISE project navigator. (Right click- >Save link as). Also change the file extension to .vhd Task s  ANDer.vhd 4-bit And-gate  ORer.vhd 4-bit Or-gate  XORer.vhd 4-bit Xor-gate  ADDer.vhd 4-bit Adder-gate  function_select.vhd Multiplexer  display_driver.vhd 7 segment driver  LEDdisplay.vhd 7 segment Multiplexer  Bit_full_adder.vhd 1 bit full adder (goes in the design of ADDER.vhd, already included)  Toplevel_lab8.vhd Toplevel VHDL code Pre Lab 1. Declare components in toplevel.vhd 2. Instantiate (port mapping) components as per design 3. Write constraints file based on toplevel Entity. 4. Set control switches(00,01,10,11) to see results of ADD,OR,XOR,AND operations Please answer the following questions and submit to your TA at the start of the lab:

Step 0: Pre- Lab 1. (Research on your own) What two different sets of operations can an ALU do? 2. (Research on your own) What’s the best use for an ALU inside a CPU pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), or Memory Write Back (WB)? 3. (Current Lab) Which operations are we program in our ALU? 4. What previously implemented components are we using to create our ALU? 5. A bitwise operator affects each pair of significant bits in the operands. The bitwise OR operation result for decimals 6 10 (0110 2 ) OR 5 10 (0101 2 ) is 7 10 (0111 2 ). What is the bitwise AND operation result for decimals 5 10 AND 9 10 ? You need to come to class with your design basics prepared. You should have a good idea of the design concept as well as some basic VHDL. In this lab we will create an ALU that implements AND, OR, XOR, and ADD functions. Create a block diagram of your top level entity showing all the required ports and components. Step 1: VHDL Tutorials If you haven't done so yet, review the following tutorials for VHDL and mudular VHDL. Pay special attention the the modular VHDL tutorial, as from now on we will use modular VHDL almost exclusively. Step 2: VHDL files  This VHDL tutorial will teach about the VHDL language, its fundamentals, and how to represent a simple circuit in VHDL.  This Modular VHDL tutorial will teach about the using components in VHDL, and creating larger entities by structural design. Add the VHDL sources above to your new project in XIlinx ISE project navigator. Go through the ALU block diagram and write VHDL code for the toplevel. Follow the structural/modular method of programming. Be very careful in mapping ports when doing component instantiation. Step 3: XDC file for toplevel After you have your toplevel.vhd file ready, you need to create a new XDC file for the toplevel inputs and outputs. Basys3_Constraints Step 4: Download to the Board Once your toplevel.vhd compiles and generates a bit file, program your FPGA as we have done in the earlier labs.

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Step 5: Evaluation Now you will want to verify that the board is operating correctly. Change inputs using the slide switches and make sure that you get the correct corresponding output. Use the mechanism you selected on the board to select operations (adding, AND, OR). If you get incorrect outputs retrace you steps making sure you have correct pin assignments and that your VHDL is correct or ask your TA. After you’ve tested circuit for proper operation including the overflow detection, show your TA. Lab Report Now write your lab report according the format your TA has outlined for you. Make sure to include VHDL codes and XDC file into your lab report. Set two 4 bit numbers on the board using SW0-SW7 Set control switches to (00,01,10,11) to see results of ADD,OR,XOR,AND operations Make a table to show which operation corresponds to which control switch combination