Lab 10 Procedure - DRIE & Ashing

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5354L

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Mechanical Engineering

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Apr 3, 2024

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EEE5354L: Semiconductor Device Fabrication Laboratory (Fall 2023) Lab 10 Procedure: Deep Reactive Ion Etching (DRIE) & Ashing 1. Pre-lab Questions: 1.1. What is the mask material in our DRIE process? Hint: what were we supposed to leave on the wafer in the last lab? 1.2. Can we get undercuts using DRIE? If yes, how? 1.3. How does DRIE obtain a deeper etch than RIE (hint: it is NOT just the plasma)? 1.4. What does SEM stand for? 1.5. How does an SEM differ from an optical microscope? 2. Lab Procedure: 2.1. Make sure the PR from the photolithography #2 has NOT been stripped off. If there is not any PR, then you cannot use the DRIE to release! 2.2. Take a 4” silicon carrier wafer and mount one 2” wafer on top of the carrier wafer, seal the edge with thermal resistant tape. The unused area on the 4’’ carrier wafer is also protected by the thermal resistant tape from being etched, as shown in the figure below. 2.3. Make sure the 2” wafer is at the center of the 4” carrier wafer to avoid breaking the wafer due to DRIE tool holding clamp during the process. 2.4. Load the wafer in the DRIE STS or Oxford Loadlock. 2.5. Set the following parameters in the anisotropic etching recipe menu. We want to etch about 15 microns. Start with the LZ_aniso recipe. The values given are approximate, make sure you record the actual values needed for your wafer. a. Etch Cycle Time – 13s b. Deposition Cycle Time – 7s c. Process Total Time – 5min d. Gas Flow Rate for C 4 F 8 , SF 6 , O 2 - 85sccm, 130sccm, 13sccm e. Pressure Values – 94 mTorr

EEE5354L Lab 9: DRIE & Ashing 2 f. RF Power Values – tool default g. Helium Cooling parameters – tool default 2.6. Once the parameters are set, load the wafer into the process chamber and run the process. 2.7. Monitor the various parameters during the process for any deviations. 2.8. Set the following parameters in the undercut etching recipe menu. We want to etch another 15-16 microns (it will etch both sides). Start with the LZ_uc recipe. The values given are approximate, make sure you record the actual values needed for your wafer. h. Etch Cycle Time - 9 min i. Deposition Cycle Time – n/a j. Process Total Time - 9 min k. Gas Flow Rate for C 4 F 8 , SF 6 , O 2 – 0sccm, 130sccm, 13sccm l. Pressure Value – 94 mTorr m. RF Power Values – default of tool n. Helium Cooling parameters – default of tool 2.9. Once the parameters are set, run the process and monitor the various parameters during the process for any deviations. 2.10. Once the process is completed, unload the wafer from the process chamber to the Loadlock. 2.11. Open the Loadlock and fetch the wafer. 2.12. Remove the tape and separate the 2” wafers from the 4’’ carrier wafer . 2.13. Now use the Unaxis 790 RIE or the TePla Asher to remove the photoresist. For the TePla Asher, 2 5-minute runs has been successful before, but more may be needed. If you are not trained on either, you may remove the PR using an acetone bath followed by an IPA bath. DO NOT rinse with DI water or blow dry, as it will damage the devices. Let the IPA evaporate. 2.14. Look at your devices in an SEM. 2.15. CAREFULLY place the wafers back into the holders, making sure not to touch where the devices are. Make sure the wafers stay with the top facing up in the box, otherwise your devices WILL break. 3. Post-Lab Questions: These are suggested questions to help guide you when writing your lab report. Do not simply answer these questions as your report. Use the posted sample lab report as a guide and incorporate your data as well as your in-lab discussions with your TA to write your report. Remember, every lab member must contribute to every lab report. 3.1. How did we etch silicon underneath our bimorph using DRIE? 3.2. As the devices are of different sizes, how does their release order relate to their lateral dimensions of the bimorphs?

EEE5354L Lab 9: DRIE & Ashing 3 3.3. Do the released bimorphs bend up or down? Why? 3.4. Are there any unreleased devices? If yes, how can we design them to release efficiently? 3.5. Can we use any wet process to etch silicon? If yes, what are the advantages/disadvantages of DRIE compared to the wet process to etch silicon?

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