LabReport3_COEN212_AnasSenouci_40132281

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Electrical Engineering

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Jan 9, 2024

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LAB REPORT III COEN 212 Digital Systems Design I Lab Section: ECAX Experiment #3: Design of (Medium Scale Integration) MSI Components Anas Senouci ID: 40132281 Lab Instructor: Afrasiabi Negar Date Performed: May 30, 2022 Date Due: June 6, 2022 I certify that this submission is my original work and meets the Faculty’s Expectations of Originality. Anas Senouci June 6, 2022

OBJECTIVES The objective of this experiment is to become familiar with word-sized versus single bit operands and to design combinational adder circuit. More precisely, the goal is to design and verify a multiplexer, a half, and a full adder circuit. THEORY It is important to understand the three main components studied in lab. The first one being the multiplexer (or mux) is a device that allows the selection of a certain input to route to the input. The Figure 1 shows how the switch from input to input is made. Secondly, the half-adder is a device that can add two single binary digits and provide the output plus a carry value. The Figure 2 shows the circuit in the component. Finally, the full-adder is a component that can add three one-bit binary numbers, two operand and a carry bit, it is designed to be able to take eight inputs to create a byte-wide adder. The Figure 3 shows a 3-bit ripple-carry adder. Figure 2: Circuit of a half adder Figure 1: Operation of a 4-to-1 mux by means of a switch analogy Figure 3: A3-bit ripple-carry adder

RESULTS Multiplexer Table I. 2-1 multiplexer truth table S IN0 IN1 OUT 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 Table II. 2-1 multiplexer truth table IN0, IN1 S 00 01 11 10 0 0 0 1 1 1 0 1 1 0 Expression (SOP): P 1 = S IN1 + S IN2 ‧ ‧ 1 IN1 2 7408 3 OUT 3 1 2 7432 2 4 6 5 7408 1 IN0 7404 S 2 1 0 Figure 4 : Multiplexer circuit

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Half-adder Table III. Half-adder truth table A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 Expression (SOP): Sum = A’B + AB’ = A ⊕ B Carry = AB Full-adder Table IV. Full-adder truth table A B C in S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Table V. Sum(A,B,C in ) k-map 1 0 3 A Sum 1 2 7486 B 1 Carry 3 2 7408 Figure 5: Half adder circuit

B 1 C in A 00 01 11 10 0 0 1 0 1 1 1 0 1 0 Table VI. Carry (A,B,C in ) k-map B 1 C in A 00 01 11 10 0 0 0 1 0 1 0 1 1 1 Expression (SOP): Sum(A,B, C in ) = A ⊕ B ⊕ C in Carry(A,B,C in ) = AC in + BC in + AB 1 A S 6 4 3 2 0 7486 5 1 7486 B C in 3 1 7408 1 2 C out 3 2 6 4 7432 5 7408 Figure 6: Full adder circuit

DISCUSSION The theoretical results listed in the lab manual were similar to the experimental results obtained showed in Table I, III and IV. In other words, the experiment was a success. QUESTIONS 1) How many rows would the truth table of a combinational 32-bit parallel adder contain? Express your answer as a power of two. State any assumptions you may have made to deduce your answer. For a 32 but parallel adder, the truth table would have 2 96 rows. The answer was deduced by assuming 32 full adders are needed for a 32-bit parallel adder with 3 inputs each (3 x 32 = 96) 2) Would it be practical to design a 32-bit parallel adder using the techniques of Boolean minimization to obtain the SOP expressions for each of the outputs? No, because there would be too many rows and data to analyse (96 inputs, 64 outputs and 2 96 combinations). 3) How many full-adders would be required to construct a 32-bit ripple carry adder? 32 full adders would be needed to construct a 32-bit ripple carry adder since 2-bit ripple carry adder need 2 full adders. CONCLUSION The mux, the half-adder, and the full-adder circuits to achieve outputs as sums and carries were made by making three sum-of-product Boolean expressions based on the K-maps of each component which were based on the truth tables. All circuits were constructed and showed expected results equal to those found theoretically.

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