2di_2021_exam_MC
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School
McMaster University *
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Course
2DI4
Subject
Electrical Engineering
Date
Jan 9, 2024
Type
Pages
16
Uploaded by ChefMorningMongoose34
Question
1
(2
points)
When
referring
to
Register
Transfer
Level
operations,
if
R
=
1101
then
what
is
the
value
of
R
after
the
following
statement
executes?
R=R>>>2;
0111
11111
10011
'
None
of
the
presented
options.
11110
Press
"Next
Page"
to
proceed
to
the
next
question.
Question
2
(2
points)
A
parity
bit
is
used
to
'
None
of
the
presented
options.
_
)
NACK
(negative
acknowledgement)
receipt
of
serial
data
)
ACK
(positive
acknowledgement)
receipt
of
serial
data
'
The
parity
bit
will
detect
if
a
single
bit
error
has
occurred
)
The
parity
bit
will
correct
if
a
single
bit
error
has
occurred
Question
3
(2
points)
Which
of
the
following
Boolean
equations
describes
the
logically
equivalent
output
F,
of
the
following
combinational
logic
circuit
X'y'z
+
X'yz
+
xy'
none
of
the
provided
options
xyz'
+
xy'y'
+
X'y
Xy
+Xx'z+2z
Question
4
(2
points)
Assuming
the
state
machine
is
currently
in
state
0
and
it
receives
an
input
of
1,
what
is
the
next
state
and
output?
next
state
=
1,
output
=
1
next
state
=
1,
output
=0
next
state
=
0,
output
=
0
next
state
=
0,
output
=
1
None
of
the
presented
options.
Analyze
the
provided
sequential
circuit
to
determine
which
of
the
following
state
diagrams
correctly
describes
the
machine
behaviour
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Question
6
(2
points)
Analyze
the
provided
sequential
circuit
to
determine
the
state
equation
of
flip-flop
A(t+1)
()
Ax
€D
Bx
()
None
of
the
pres
()
(A+x)(B
+x)
()
Ax
+
Bx
()
AX'
+
Bx’
Question
7
(2
points)
Analyze
the
provided
sequential
circuit
to
determine
the
state
equation
of
flip-flop
B(t+1)
|
D
A
>
>
Clk
1>
Clh
.
)
None
of
the
pr
()
Bx
()
A'x
6BB'x
Question
8
(2
points)
Given
the
following
word,
10101100,
what
would
the
parity
bit
value
be
if
using
odd
parity:
)
not
enough
information
to
determine
parity
bit
value
Question
2
(2
points)
In
the
following
block
diagram
each
register
holds
4-bits.
Initially
register
A
has
the
value
1010
and
register
B
has
the
value
1101
If
Shift
control
is
logic
1,
then
what
is
the
value
of
register
A
after
2
clock
pulses?
SI(-'
S()'
_S.IR
3()0?
*1
Shift
register
A
»1
Shift
register
B
f——
A
4
CLK
CILA
Clock
w—
\
Shilt
—
/
control
1
0001
)
0101
11010
)
None
of
the
presented
options.
)
1101
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Question
10
(2
points)
In
the
following
block
diagram
each
register
holds
4-bits.
Initially
register
A
has
the
value
1010
and
register
B
has
the
value
1101
If
Shift
control
is
logic
1,
then
what
is
the
value
of
register
B
after
4
clock
pulses?
Note:
Ignore
pulses
from
similar/related
questions
A
SO,
Sl
SO,
——{
Shift
register
A
*1
Shift
registor
B
pf——
‘
i
I.N
CLK
1l
Click
==
\
Shilt
—
/
control
)
1101
)
0001
0011
)
None
of
the
presented
options.
)
1010
Question
11
(2
points)
Which
of
the
following
Boolean
equations
describes
the
minimized
sum-of-product
output
of
G
in
terms
of
the
input
vanables
of
the
above
combinational
logic
circuit
a—>o
)
'
>
=
O
(
)AD
+
ABC
+
BCD'
()
AD
()
(A"+
BC)A+D')
(
JA'D'+
ABC
(_)
None
of
the
presented
options.
'
Question
12
(2
points)
Which
of
the
following
Boolean
equations
descnbes
the
minimized
sum-of-product
output
of
F
in
terms
of
)
the
input
vanables
of
the
above
combinational
logic
circunt
A=
D,
)
>
AD’
(A'+BCYA'(A'D))
A'D
+
BCD
None
of
the
presented
options.
A'D
+
ABC
Question
16
(2
points)
How
many
32K
x
8
bit
RAM
chips
are
needed
to
provide
a
memory
capacity
of
256K
bytes?
()
Unknown
Question
17
(2
points)
Consider
the
Register
Transfer
Level
operation
below.
If
the
initial
value
of
R1
1s
0010
and
the
initial
value
of
R2
is
0001,
what
is
the
value
of
R3
after
the
next
clock
edge?
R1
<=
R1
+
R2;
R3
<=
R1;
0001
0100
Unknown
0011
0010
Question
19
(2
points)
In
Register
Transfer
Level
operations,
“case”
statements
are
translated
into
what
type
of
hardware
by
the
logic
synthesizer?
'
Flip-flops
)
Multiplexers
)
Registers
)
IF
statements
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=
Question
2V
(2
points)
Assuming
the
state
machine
is
currently
in
state
AB=11
and
it
receives
an
input
of
1,
what
is
the
next
state?
-t}
Q
A
DD
-
r
-
|
i
1
J
Q
b
L
K
L/
11
10
01
00
None
of
the
presented
options.
COE2DI4
Midterm
Test
2
Multiple
choice
questions
(numbered
1
to
20)
-
indicate
your
answer
by
filling
the
corresponding
circle
on
the
OMR
answer
sheet
Output
Input
Clock
Figure
1
-
Circuit
for
question
1.
1.
The
circuit
show
in
Figure
1
is
designed
using
two
multiplexers.
This
circuit
is
equivalent
to:
1.
a
positive
edge
triggered
T
flip
flop
o
]
o
ey
bis
o
moodoy
o
iy
oy
mgmo
o]
Tl
Flo
e
2.
We
would
like
to
use
a
T
flip
flop
and
design
a
circuit
that
works
like
a
J-K
flip
flop.
The
simplified
input
to
the
T
flip
flop
should
be:
1.
T=J=K
2.
T=JQ'+K'Q
3.
T=JQ'+KQ
4.
T=JQ+KQ'
5.
We
cannot
build
a
J-K
flip
flop
USiII
3.
How
many
4-to-1
multiplexers
are
needed
to
implement
a
64-to-1
multiplexer?
/
Page
3
of
11
COE2DI4
Midterm
Test
2
4.
How
many
4-to-16
decoders
are
needed
to
implement
an
8-t0-256
decoder?
Note,
all
the
decoders
have
an
enable
input
and
all
the
inputs
and
outputs
are
un-inverted.
5.
What
is
the
output,
f(a,b,c,d),
for
the
circuit
of
Figure
27
I
6
__alnln
\
9
fl‘:b'c)d)
’
U
O\
D1
’U
%
I
)]
6
YV
8
c1(d
!
)
&
V
Elptrd
"
|
&
0
|eeor0
;)
0
(|e>10
Figure
2
—
Circuit
for
questions
5.
)
I
O
frel
o0
6.
What
is
the
output
for
the
following
l:ircuit?
—
4
[
‘V/"—
\\
A
o
a—
I%igure
3
—
Circuit
for
questions
6.
Page
4
of
11
Your preview ends here
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COE2DI4
Midterm
Test
2
7.
What
is
the
output
for
following
circuit?
N
N
N
k-
R
8.
Which
of
the
following
statements
is
correct
for
the
following
circuit
after
using
the
shown
clock?
2151)
D
Q
>
Q
18]
e
Lo
|
>
2141
Clock
a
Figure
4
—
Circuit
for
questions
7.
v
doj4
di4
D
QF
I
|
pe
_>
%
Qo
|
Clock
Figure
5
—
Circuit
and
clock
pulse
Clock
___|
for
questions
8.
e
but
indeterminable.
Page
5
of
11
COE2DI4
Midterm
Test
2
|
enable
O
—
clock
Figure
7
-
Circuit
for
question
12.
12.
In
Figure
7,
if
enable=1
and
the
current
(or
present)
state
is
Q3Q2Q1Q=0101,
then
the
next
state
will
be:
N
0—
D2
Q:
I~
4
D2
Q2
r
|[1—o:
Q2
—
Up
b
—
Up
|
Up
0
D’countero'I
'i
0
D't:aunterQ1
.I
0
D‘wunterQ1
1—
Do
Qo
|—
1—
Do
Qo
1—
Do
Qo
f—
Load
\J
Load
Load
clock—
clock—
clock—
(a)
(b)
(c)
(d)
Figure
8
-
Circuits
for
question
13
(it
is
assumed
that
after
power
up
the
state
is
001).
13.
Using
an
up
counter
with
parallel
load
capability
(Q,
and
D,
are
the
most
significant
bits)
we
can
generate
a
counting
sequence
1,
2,
3,
4,
5,
6
using
the
circuit
shown
in:
BaseZoll)
8:51
AM
Tue
Dec
13
Insert
i
2.
Flip
flops
will
swap
their
outputs.
3.
Outputs
for
both
thp
flops
will be
1.
4.
Outputs
for
both
flip
flops
will
be
the
same
but
indeterminable.
5.
None
of
the
above.
Page
S
of
11
0‘\
\d\fi
COE2DI4
Midterm
Test
2
-
\&\‘
clock
|
din
9
din
Ghan
wave
’
[
o
wave
3
I
'l
I
|
|
I
.[_|
[E_
wave
6
I
I
'
I
|
Ke
Qcf~
wave
7
|
'b\“S
wave
,
I
Q/A(/
:
!
(b)
“\)
'(()NV/
Figure
6
-
Sequential
elements
and
output
signal
waveforms
for
questions
9,
10
and
11.
Note,
the
sequential
elements
are
assumed
to
be
ideal,
i.e.,
the
propagation
delay
and
setup
and
hold
times
are
considered
to
be
zero.
9.
Given
the
clock
and
d;,
waveforms
in
Figure
6(b)
the
waveform
for
Qa
from
Figure
6(a)
is:
10.
Given
the
clock
and
di,
waveforms
in
Figure
6(b)
the
waveform
for
Qg
from
Figure
6(a)
is:
1L
wave
4
from
Figure
6(b)
11.
Given
the
clock
and
di,
waveforms
in
Figure
6(b)
the
waveform
for
Q¢
from
Figure
6(a)
is:
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hi
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