LAB2 ECE 260A Q2

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Electrical Engineering

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Jan 9, 2024

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Name: Kumar Divij PID: A69028007 Name: Ishan Bansal PID: A59025917 Question 1 Hand analysis 1.(a) Let the number of stages be N. C L = 500 fF ; Time Period = 10 ns; t r , t f = 0.1 ps; GateCap = 1 fF NMOS size: W L = 90 nm 50 nm ; PMOS size: W L = 135 nm 50 nm ; Sizes are provided according to mobility ratio. C ¿ = 1 fF 1 um ∙ 90 nm + 1 fF 1 um ∙ 135 nm = 0.225 fF G = 1 ; B = 1 ; H = 500 fF 0.225 fF = 2222.2222 ^ f = ( GBH ) 1 N = F 1 N Minimum delay = ∑ i = 1 i = N F 1 N + ∑ i = 1 i = N p = N ⋅ F 1 N + N ; ( p = 1 ) d dN ( N ⋅ F 1 N + N ) = 0 ; N = 6.0277 ; N = 6 1.(b) If the sizing provided for PMOS (W=135nm) and the sizing provided for NMOS (W=90nm) is done according to ratio of mobility for NMOS and PMOS then the inverter built will have equal rise and fall propagation delays. Simulation 1.(c)

Figure 1.1 Simulation of inverters N=1 to N=6 Figure 1.1.1 N=1 to 6

Figure 1.2 N=1, N=2 Figure 1.3 N=3,N=4 Figure 1.4 N=5, N=6

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C ¿ = 1 fF 1 um ∗ ( 90 nm + 135 nm ) = 0.225 fF ^ f = ( GBH ) 1 N = ( 500 0.225 ) 1 / N Table 1: Inverter Performance Summary N f tpdf (ns) tpdr (ns) tpd (ns) Power(uW ) PDP(uW*ns) EDP(uW*ns*ns ) 1 2222.22 2 2.504 1.572 2.038 32.8 328 3280 2 47.1404 5 0.2129 4 0.2066 3 0.20978 5 55.97 559.7 5597 3 13.0495 6 0.1048 1 0.1055 3 0.10517 72.02 720.2 7202 4 6.86589 0.0845 0.0886 6 0.08658 96.13 961.3 9613 5 4.67043 7 0.0859 6 0.0920 7 0.08901 5 125.5 1255 12550 6 3.61241 7 0.0975 5 0.1029 0.10022 5 249.1 2491 24910

Question 2 Hand analysis 2.(a) Yes both the circuits have the same logic function F =( ´ ABCD + E ) 2.(b) Ignoring the second order effects, the equivalent output resistance generated by resistor- capacitor model of a transistor would come out to be same for both the CMOS design. Taking the mobility ratio σ = μ n μ p and resistance of least sized transistor be R , then resistance offered by each of the pull-up transistors is σ ∙R 6 and resistance offered by each of the pull-down transistors is σ ∙R 4 . So net resistance in both cases come out to be same . 2.(c) For worst case pull up resistance we can assume that E = 0 and only one of A,B,C,D = 0, so that gives the pull up resistance to be 3 R 6 + 3 R 6 = R = 15 k Ω The input combination which results in a low output and offers the least resistance is 4 ∙ R 4 ∨ ¿ R = R 2 The value of the resistance is R 2 = 15 2 = 7.5 k Ω 2.(d) The output that cause output to be high is E = 0 and any of A,B,C,D = 0. For lowest (best case) resistance input combination will be: A = 0 ,B = 0 ,C = 0 ,D = 0. So, the output resistance will be: 3 R 6 + ( 3 R 6 ∨ ¿ 3 R 6 ∨ ¿ 3 R 6 ∨ ¿ 3 R 6 ) = 5 R 8 = 9.375 k Ω 2.(e) C Load = 120 fF t plh = 0.69 ∙R pull − up ∙C Load ; t phl = 0.69 ∙ R pull − down ∙C Load Best Case Worst Case Resistance Time Resistance Time Pull Up 9.375 k Ω t plh = 0.776 ns 15 k Ω t plh = 1.242 ns Pull Down 7.5 k Ω t phl = 0.621 ns 15 k Ω t phl = 1.242 ns 2.(f) Circuit B will perform better if it is known a priori that E will arrive the latest. Let us consider the following transition. Lets say A,B,C,D are transitioning ( 1 → 0 ) and E is 1 → 0 . Then in Circuit A the parasitics associated with A,B,C,D can’t be charged to V DD until E arrives(to 0). So as soon as E arrives(to 0) there is huge load on the transistors to drive the parasitics to 0. This slows down the performance and reduces speed. But in Circuit B the parasitic nodes of A,B,C,D can pre charge to 0 and when E arrives (to 0) only the nodes related to E has to be charged to V DD which saves time and thus increases the performance.

2.(g) (Worst t plh ) Let’s consider previous input set to be: A,B,C,D,E = {1,1,1,1,0} so the capacitances associated with nodes Z,W,V,Y,X are all discharged to 0. Let the current input be A,B,C,D,E = {1,1,1,0,0} so now transistors with D & E have to charge Z,W,V,Y & X to V DD . (Worst t phl ) Let the previous input set be A,B,C,D,E = {1,1,1,0,0}. So in this case capacitances at X,Y,Z,W,V are all charged to 1 and D&E are off so output is 1. Now if the current input set is A,B,C,D,E = {0,0,0,0,1} then the smallest transistor E of size 1 must discharge all these nodes. Previous Current Worst t plh A,B,C,D,E = 1,1,1,1,0 A,B,C,D,E = 1,1,1,0,0 Worst t phl A,B,C,D,E = 1,1,1,0,0 A,B,C,D,E = 0,0,0,0,1

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Simulation Figure 2.1 Worst Case simulated t plh = 0.7375 ns ; Worst Case simulated t phl = 1.7147 ns Figure 2.2 General simulated t plh = 0.597 ns ,t phl = 1.75 ns

Question 3 3.(a) Electrical Effort (H) = H ; Branching Effort (B) = 1 ; Logical Effort (G) = 8/3 * 1 ; Parasitic Delay (P) = 6 + 1 = 7. F = G * H * B = 8H/3 f = (8H/3) 0.5 D = 2 * 2 * (2H/3) 0.5 + 7 D = 4 * (2H/3) 0.5 + 7 3.(b) Electrical Effort (H) = H ; Branching Effort (B) = 1 ; Logical Effort (G) = 5/3 * 5/3 ; Parasitic Delay (P) = 3 + 2 = 5. F = G * H * B = 25H/9 f = 5/3 * (H) 0.5 D = 2 * 5/3 * (H) 0.5 + 5 D = 10/3 * (H) 0.5 + 5 3.(c) Electrical Effort (H) = H ; Branching Effort (B) = 1 ; Logical Effort (G) = 4/3 * 7/3 ; Parasitic Delay (P) = 2 + 3 = 5. F = G * H * B = 28H/9 f = 2/3 * (7H) 0.5 D = 2 * 2/3 * (7H) 0.5 + 5 D = 4/3 * (7H) 0.5 + 5

3.(d) Electrical Effort (H) = H ; Branching Effort (B) = 1 ; Logical Effort (G) = 5/3 * 1 * 4/3 * 1 ; Parasitic Delay (P) = 3 + 1 + 2 + 1 = 7. F = G * H * B = 20H/9 f = (20H/9) 0.25 D = 4 * (20H/9) 0.25 + 7 3.(e) For H = 1: D a = 10.266; D b = 8.33 ; D c = 8.528; D d = 11.884 For H = 10: D a = 17.328; D b = 15.541 ; D c = 16.155; D d = 15.685 For H = 25: D a = 23.33; D b = 21.67; D c = 22.638; D d = 17.92 Thus, we select model B for H = 1 and H = 10 , while we should select model D when H = 25 to ensure minimum delay.

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Question 4 4. Optimize the circuit to obtain the least delay along the path from A to B. Answer. The path logical effort is G = (4/3) 3 . The branching effort at the first stage’s output can be seen as (y + y) / y = 2. Branching effort at the output of the second stage is (z + z + z) / z = 3. Thus, the branching effort is B = 2 * 3 = 6. Electrical Effort (H) = 4.5 => F = G * B * H = (4/3) 3 * 6 * 4.5 => F = 64 Thus, f = 64 1/3 = 4. Now, f 1 = 4/3 * h 1 = 4 => h 1 = 3. Similarly, h 2 and h 3 = 3. Now, h 3 = 4.5 / z = 3 => z = 1.5C Similarly, h 2 = 3z / y = 3 => y = 1.5C Final Answer: y = 1.5C, z = 1.5C