ELEC 2607 Lab 4

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Carleton University *

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2607

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Electrical Engineering

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Jan 9, 2024

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ELEC 2607 – Switching Circuits Lab Section: L2E Wednesday 2:30-5:30 Laboratory #4 A MIDI INTERFACE Report by: Student Name: Sharran Sivakumar Student Number: 101150347

1.0 Introduction The purpose of this laboratory was to design a MIDI interface circuit. A MIDI is the name for a digital interface used in electronics. MIDI is an interface, where the bits come in one after the other in certain orders. The keyboard sends out a 10-bit word, containing 8 bits of data called a data byte and two control bits (start and stop). The signal is sent out serially, one bit following another. The start and stop bits are used to tell the interface when to start or stop listening. The designed circuit was built on Xilinx, simulated using ModelSim, and implemented on a Complex Programmable Logic Device. This lab report will further discuss the design specifications, the actual design process, and the final implementation and testing of the MIDI interface. 2.0 Specifications A MIDI interface circuit consists of 7 different sub-circuits. These sub-circuits are the FindStart, Last4Samp, Majority, CountClear, SampCount, BitCount, and the Ser2Par circuits. The circuit receives a 10-bit serial word input signal from a keyboard, and outputs an 8-bit parallel data byte by sending it out bit after bit to some musical instrument like a mixer. First, a serial input signal consisting of a START bit, 8 data bits, and a STOP bit will be sent in. There should be a small gap in time between words of indefinite length. To achieve optimization, the receiver takes several samples inside each midi bit. The Last4Samp circuit captures a sample on every active clock edge and holds the last 4 samples. The FindStart circuit checks the samples for 3 zeros out of 4 samples and sends out GoStart when this is found. The Majority circuit sends out the majority value of the last 3 samples. The CountClear also checks that this was not just a low data bit by checking the bit counter, if BitCount, is sending out BIT9 indicating the last known input bit was a STOP bit. If these conditions are met, the ClrSampCount goes low. Then, the SampCount circuit rests at a count of zero and starts counting up about halfway through the START bit. It counts 0,1,2,3,4,5,6,7,0,1,2…. Sending out a GRAB9 pulse during each 7 th count. GRAB8 is the same as GRAB9 except the last pulse is removed. The BitCount circuit keeps track of which bit has been reached in the midi word. It counts the number of GRAB9 pulses generated by SampCount, thus it counts 8 bits plus the STOP bit. Its BIT8 signal is used to remove the final GRAB9 pulse, to change GRAB9 into GRAB8. This lets the Ser2Par circuit save only the data and not the STOP bit. BIT9 is high after all 8 data bits have been captured and is used as a DataValid signal to show the data is stable and can be read. Finally, the Ser2Par

circuit responds to each GRAB8 pulse and transfers the data bit values from MAJ to the seven parallel data outputs. Gates can be used freely no matter what type they are or how many of them are needed. The design will be constructed on Xilinx and simulated on ModelSim. The ModelSim software will generate waveform representations of the MIDI interface behaviour. 3.0 Design The general circuit being designed looks like the figure below: Figure 1.0: Diagram of MIDI Interface The Last4Samp Circuit: When the serial MIDI signal is received as a 10-bit input word, the Last4Samp circuitry takes this input and captures a sample on every active clock edge. Then it only holds the last 4 samples of each bit and sends them out as S3,S2,S1,S0. This is usually done through shift registers. Figure 2.0: Shift Registers

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The upper shift register takes a sample of S at every active clock edge and stores it in the leftmost flip flop. On the next edge it shifts the previous sample right and stores a new sample. When the simulation starts, the reset signal will clear all the flip flops. Inverters are needed in the design for the fact that if inverters are placed before and after each flip flop that is the only way to get the proper output without changing the reset signal. Therefore, the Last4Samp circuit design is like the figure below: Figure 3.0: Last4Samp Circuit The FindStart Circuit: The input of the FindStart circuit is the last four samples from the Last4Samp circuit. The circuit checks the samples for three zeros out of the four samples and outputs GotStart. GotStart becomes high only if three of the samples are equal to zero. Using this information an equation for GotStart was derived: S 0 S 2 S 3 + S 0 S 1 S 2 + S 1 S 2 S 3 + S 0 S 1 S 3 The derived expression above was then used to design the FindStart circuit below:

Figure 4.0: FindStart Circuit The Majority Circuit: The majority circuit is responsible for sending out the majority value of the last 3 samples. The possible combinations for S where the majority value would be given were 011,101,110 and 111. The simplified expression to obtain these values of the majority signal was then derived: S 2 S 3 + S 1 S 2 + S 1 S 3 The final simplified expression above then helped design the majority circuit below: Figure 5.0: Majority Circuit

The SampCount, BitCount, and CountClear Circuit: The SampCount circuit counts from 0-7 and then repeats. It should have an input which when high sends the count to 0 on the clock edge. On the count of 7 it should send a GRAB pulse one cycle long. The SampCount circuit was designed using D flip-flops. The steps of the design are shown below:

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Figure 6.0: SampCount Circuit Design Steps Therefore with this information, the SampCount circuit could be visualized below: Figure 7.0: SampCount Circuit Design

The BitCount circuit counts the data bits and the stop bit. This results in 4 flip flops being needed for a total of 9 bits. The input is the GRAB pulse, and it has two outputs. One is high during the eighth count and one is high during the ninth count. The BitCount circuit and SampCount circuits are very similar with the only difference being the SampCount has 8 states while the BitCount has 9 states. The design steps to design this circuit can be shown below: Figure 8.0: BitCount Circuit Design Steps The BitCount circuit keeps track of which bit has been reached in the midi word. It counts the number of Grab pulses generated by SampCount. The Bit8 signal is used to remove the final Grab pulse and ultimately changes Grab9 into a Grab8. Bit9 is high after all 8 data bits have been

recorded and is used as a DataValid signal to tell the outside world that the data is stable and can be read. The BitCount circuit could be visualized below: Figure 9.0: BitCount Circuit Design The CountClear circuit checks if the GotStart signal is a ‘1’ indicating it has found a valid start bit. It also checks that this was not just a low data bit by checking if the bit counter, BitCount, is sending out Bit9 indicating that the last known input bit was a stop bit. If Bit9 is high and GotStart is low the ClrSampCount goes high. To prevent unwanted clears, a fix signal was made to make sure the signals were low up until Bit9. Therefore, the schematic of Countclear looks

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like the circuit below: Figure 10.0: ClearCount Circuit Design The Ser2Par Circuit: The Ser2Par circuit performs the final stage of our MIDI interface circuit. Only when Grab8 is high, it collects all of the eight serial data bits and sends them out in order. The circuit will be using flip flops to act as shift registers. Eight flip flops will be needed in order for the circuit to remove all eight bits as that is the goal. The Ser2Par circuit could be better visualized below:

Figure 11.0: Ser2Par Circuit Design Now with all the aspects of the MIDI interface completed, the complete circuit can be visualized below: Figure 12.0: MIDI Interface Circuit Design 4.0 Implementation and Testing After designing the circuit, it was then simulated through Xilinx and ModelSim. To make sure that there were no errors in the schematic designs each block was implemented separately. Each

of the blocks were simulated separately using the available test fixture files. After no errors were found, a test file to simulate the entire MIDI interface was run. The MIDI interface was run, and the waveforms were generated. Initially, the waveforms were not correct as they produced red and blue lines which should not have been there. However, after making a few changes the right simulation of the waveforms was then produced, however there was still a small error as red lines kept appearing which can be seen below: 5.0 Conclusion A MIDI interface circuit was designed and implemented with a few errors. All of the necessary objectives of the lab were met within the required guidelines. At, first the constructed circuit encountered various problems when simulating. After making some changes to certain gates and wiring paths the waveforms were then simulating in the correct fashion. However, when trying to simulate the waveforms for the entire MIDI interface red lines kept appearing, therefore insinuating that there is an error somewhere. This problem ultimately was not able to get fixed as the error was not able to be found. Also, during this lab an important conclusion that was made was the FTCE flip flops do not act in the same was as FDCE flip flops, although they are very similar. Nonetheless, the MIDI interface lab was interesting, especially with gaining further

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knowledge about the subject. This MIDI interface can be also compared to an everyday instrument such as a piano as the output could be similar to keys pressed on a piano. References: [1] M.Shams: Laboratory 4: A MIDI Interface, Department of Electronics, Carleton University,March 5. 2021. Appendix Last4Samp Waveform

Majority Waveform FindStart Waveform

BitCount Waveform CountClear Waveform

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