ELEC4601 CRIB 2-merged

Question 1 0/1point Question 2 O S e R Questi.onS ' . 0/1poiht Question 6 pre-charged? A de is running in the main thread ARM p ;and th broutine is called. As partof Choose all of the following devices that are appropriate 12C slaves. he DMA controller st directly the subroutine call: elect a ‘ tzef0 00 1 Word Line _ Word Line _ l"lULt))U 14 B} LIe Suprouunc are pushed onto th sack Temperature sensor with SPI interface ’ . None of the other answers are correct. 2 b the ' o ! e S e solid state drive § g » 8 Bl P @ c.the target periph Gnd 8 5 Gnd @ proc.:»u, flags are pushed onto the stack, the link register is pushed onto the stack, and the = None of the other answers are correct. — . L holdi t for tt k ti hed onto the stack . Word e None of the other answers are correct (=] St L . . = . e . Bluetooth module with UART interface @ e datat Thié Capacitor The link ICBIDI.CI ) g 14 the subroutine 1 byte . . f. address bus i A are pushed onto the stack IMU with SPI interface - i e 2N where N is the width of the data bus Th t hed onto the stack, and tt v‘ ters holdi g ters for the . = O Bitline logy(N) where N is the width of the data bus subroutine are pushed onto the stack hard disk drve 2 bytes Suppose your manager decides to install only 512KB of main memory and 2KB of cache (e.g. 2!! = Question 9 Question 10 Question 11 0/1poie Qe oo H hard M4 ller? When ch th t lue of 12C pull t e i e | saae . i How many hardware ted stacl ilable in the C icr r en choosing the resistance value o ull-up resistors: lave then: In our labs when you wrote code for the Cortex M4 microcontroller, compiled it, Hich . d i L e Y pp Cortex M4 microcontroller? g p p slave then : . i 7 - 7 None of the other answers are correct. the microcontroller, the code was stored in: > Which type of bus would you expect to be faster? Full duplex, or half-duplex Two = () None of the other answers are correct. - pulls its SCL pin low to release control of the bus. = Flash memory £ Half duplex Eight size them larger to reduce current flow during the idle bus condition. pulls its SDA pin high to release control of the bus. | N AU LR e SRAM One 1 1 H o Full duplex size them larger to increase 12C bus bandwidth. . ] : ¥ Hide question 11 feedback it , None of the other answers are correct. size them smaller to ensure a logic zero can be transmitted. St Roria oF the s e o ok None of the other answers is correct. The slaves have to always lsten to the bus, s0 they can't go into tri-stat One of the other answers are cofrect, Four size them smaller to decrease overall power consumption during bus operation. Boot firmware Question 15 T 0/1p Question 17 Question 14 0/1po The f°||ow|ng code appeared in Lab 4. What did the line "x = (k+1)% The following line of code is from your third lab. What does it do? Ina big endian computer, the most Significant byte of a Word gets stored at: Question 12 0/1point The LR (link register) found in ARM M4 mi llers directly ponds to the X86 reg (sizeof (note) /sizeof £ (float)) ;" do? GPIOB->0DR “= ODR (RED_LED) ; _ L amed: a higher address than the least significant byte Six devices share an 12C bus. Three masters, and three sIaves Slave #1 has address 1001001, slave #2 has pC address 1001110, and slave #3 i 1001010 All at th time, Master #1 attempts to i errupt Service Routine ) None of the other answers are correct. None of the other answers are correct. F A S R e S T e communication with Slave #1, Master #2 attempts t ication with Slave #2, and Master #3 DI g Ponine i e T olene = ~ alower address than the least significant byte attempts to communication with Slave #3. Which Master and Slave take over the bus? sp i i PONCINg cs It sets the GPIO used for the red LED to "pull-down" mode. depends on the programmer » [ Master #1 and Slave #1 o () It inverts th | e b e e e ER e = None of the other answers are correct. ' ' the same address as the least significant byte Master #2 and Slave #2 sl da oloul inputs from Master #3 and Slave #3 */ _ Lol 0/1pein Question 22 speaker.period(note [k] i PP P, - T L TRV Question 19 0/1pc Senefachi: ae m’ e e that the Slave did ive the address data from the Master. However, if the Slave did ivethe With respect to the "Iron Law", pipelining is used in CPUs and microcontrollers to reduc Question 18 0/ 1 point tecides to impl he circui L ; It. As long as the speaker = vol/2; 5 address data, then joes it } d the NACK? It's drivi fuci i WHO SENDS . >Fl sens e 5 [ U= BECR T Y B Y B R T Y S E Y THE NACK? Your logic analyzer g8 he ADDR lue is 6723H and the DATA lue is 0055H. The k = (k+1)%(sizeof(note)/sizeof(float)); ’ = cycles per instruction term MEMWH# signal | EMR signal Which g ig | the logi } the slave does actually send the NACK analyzer, assuming DS=600? = no device sends the NACK instructions per program term MOV 0055H, 6723H * * sets k to equal si £( ) /si (float) the bus arbiter generates the NACK i b e o S ; None of the other answers are correct. o ()MOV [723H], 0055H SLAVE #1 SLAVE #2 adds {1tk to k, Yy ( ) / ( ) g p MOV 723H, 0055H Chooses a random note to play next None of the other answers are correct. time per cycle term MOV [6723H], 0055H adds 1 to the value of k ¥ Hide question 20 feedback None of the other answers are correct. = i ts the index into tf t y but keeps it within tt y by pping it t No one sends a NACK. It is the absence of a signal. MOV OOSSH, 7238 =» TIIO, this V\ti" nOI': work and @Spartan should be chastised. None of the other answers are correct. Question 29 o / 1 pc Yes, this looks great and @Spartan should get a big raise! Question 28 0/1poi You memory decoding. Your address bus is 64 bits wide. You decide to use four address Question 25 0/1] < tide question 19 feedback In our lab ird looking function called " wfi()". What was this weird looking function doing? lines for CS# (chip select) signals. You are using 16K X 8 DRAM ICs. How much memory in total can you Suppose SP=400H, DI=0400H, BP=EODFH, AX=EEFFH, BX=1001H, and CX=1234H. If the following | lect issing. Fi . ) o address with this scheme? Express your answer in KB where one KB is 1024 bytes. sequence of instructi Lo okt e 4 f f SP? it enables the interrupts for the joystick Question 27 0/ 1 point it detected the button | quence to blow up the chonker civilization Answer: x (64) FUSH O None of the other answers are correct Et}’z: AD)'( Suppose you write some firmware for an ARM processor but the compiled code is too large to fit into the e e S PUSH BX available memory of the microcontroller. One option is to target the Thumb-1 instruction set in order to be i : . i . | Sae e if (done == 0) i : A : : i . it puts the microcontroller to sleep . . . L _ POP DI able to fit the code into the available RAM. What is the negative consequence of doing this? Bits 2y:2y+1 OSPEEDRy[1:0): Port x configuration bits (y =0.15) . : POP CX y 9 tput sp esitia = The performance is generally reduced . 01: Medium speed PUSH BP . Question 31 10: High speed 03FCH 11: Very high speed o @OTrain is building a computer from scratch. @OTrain knows the memory access times will be A EEEFREEO" SOCFEFEEFrOt ‘EFEREREOL . * . * M * . *?2 * * * * * ocess will waste cycles waiting for data from the external memory. What should be includec e x| X ) Answer: % (*interrupt®, *handler*, *ISR*) Question 30 0/ 1 point desngn to alleviate this issue? ¥ Hide question 32 feedback . . . . . . . . . * * * Q ion 37 0/ 1 poin You have a cache with 2048 indexed locations, 6 tag bits per location, and the cache line size is 16 bytes. If Answer: x (*cache®, "DMA’) You want the GPIOs set to low speed so that C dv/dt is low, which means cross talk is low. - o o ,po t the cache directly maps the entire address space of the processor, how many bits are used in the address D A oty bus? M [T JafsTaTsTel vl ] SCK(cPoL=0) Answer: % (21) Questiona> 071point The unrolled code does the same thing as the code with the loop, except it doesn't use any jumps, so it 'II I When using an ISR for high speed p ing of data that is received through an interrupt . - i ik eneniopiinbada tu e le of this in our lab with the ShOUld run faster. However, if the counter for the loop is very large, what principle of effective cache - .Il ‘.‘. Question 33 0/1point chonker wheel. operation is violated? . Il.llllilll‘.ll‘l. Answer: % (*latency”) The link register (LR) in the Cortex M4 stores the return address when a subroutine is called. This avoids | : Answer: % (*spatial locality®) Aiaher % (S OxES.Loh 111001019 using the stack and the overhead (latency) associated with stack manipulations. Is there every a case where T e e e the LR must be stored on the stack? Explain in a sentence. Latency s Question 41 0/ 1 point Answer: % (*nested®) Normally we think of stealing as a bad thing, but when it to how DMA (direct y access) works, Question 42 g : cycle stealing is a GOOD thing. True or False? Question 39 QUQStIOfl 40 The big advantage of two-way associate cache is that it does not require tag bits. True or False? True Fill in the blank: In general "saturation arithmetic" is useful for applications. ' True e b sl el e e What is the type of memory used for L1 cache? = () False - . * * kei * ino* = alse Answer: x (*DSP*, *signal*processing®) . o e . . ¥ Hide question 41 feedback Answer: % (*SRAM®, *static ram*, *on-chip*, on chip) . - 1 + 1 Cal ] vy | H + A 14 P L 1:6¢, + th At | ¥ Hide question 39 feedback i b A i Flowever dents tooka difterent view rgiinip. 1. Calculate the Tag: even t..cug.. cycle g I th text p with cycle . . S g the computer system should be faster. * Since it's a fully associative cache, the entire address is used as the tag. DSP ......... but if you wrote something you think is correct let me know. T ’ ' ' et RN s " * Tag bits (all bits): "10101100110011° L 5 KB of main e and 2KB of cache ( g 0o . . So l have to dglicc vvull tat ! 4 Y P LIS quUESLION. 2048 cache locatlons) Under these constramts, answer the followmg in the B oxes prov1ded g 2.1 Che(:klng the Cache for a Hit . . 2. Comy with Cache Tags: 1. [1 point] Assuming full decoding, | o Idress li der to The process of checking if a given 14-bit physical address is present in the cache involves the following steps: 2.1 Checking the Cache for a Hit * Check all cache lines to see if any have a matching tag. address all of the installed main mem(’\y The process of checking if a given 14-bit physical address is present in the cache involves the following steps: * Assume Cache Line O has the following information: 5\1' \o2 ¥ 1. Extract the Tag: From the 14-bit physical address, the cache controller first extracts the 2 most ' ; ki ‘ \D L D significant bits as the tag. For example, if the physical address is 11011001100101, the tag would be 1. Extract the Tag: From the 14-bit physical address, the cache controller first extracts the 2 most * Cache Line O Tag: "10101100110011° — signiican 1LS as € tag. ror exampile, 1 € pnysic ress 18 ’ e tag wou e 2" 4. ¢ = | a‘ ificant bits as the tag. F le, if the physical address is 1101100100101, the tag would b 2 * Valid Bit: 1" (assuming valid) 2. Identify the Index: The next 10 bits of the address specify which cache-line to look in. Continuing 2. Identify the Set Index: The next 8 bits of the address specxfy which set to look in. Continuing with 2. Determine Cache Hit or Miss: with our example, the next 10 bits are 0110011001, which is the index. our example, the next 8 bits are 01100110, which is the set index . . ) N ) - [1 point] If direct-mapping cache is used, how many bits are required for the index? * Ifthe tag in the address matches the tag in any valid cache line, it's a cache hit. 3. Check the Cache Line in the Identified Index Location: The cache controller now examines 3. Check the Cache Lines in the Identified Set: The cache controller now examines each of the four . , s . . the cache line at the index location. It compares the tag bits of the address with the tag bits stored in cache lines within the identified set. It compares the tag bits of the address with the tag bits stored in If there’s no match or the valid bit is not set, it's a cache miss. logz 1046 = q v 2 2-\o0 Z'P the cache line. each cache line. . " . 4. Det ine Cache Hit Miss: ! 1.\ o - L\ 4. Determine Cache Hit or Miss: e e e e i ) ) ) ) ) e Cache Hit: If the tag in the address matches the tag in one of the cache lines and the valid bit When choosing the resistance value of 12C pull-up resistors: e Cache Hit: If the tag in the address matches the tag in the cache lme, it’s a cache hit. The of that line is set, it’s a cache hit. The controller then uses the byte offset to retrieve the specific R~ e o iR Ui . i [1 point] If direct-mapping cache is used, how many bits are required for the tag? control}er then uses.the byte offset taken frorh the two least significant bits of the physical address byte from the cache line. R to retrieve the specific byte from the cache line. e Cache Miss: If none of the cache lines have a matching tag or if the valid bit is not set, it’s a - . ) : : e Cache Miss: If the cache line does not have a matching tag, it’s a cache miss. The controller cache miss. The controller must fetch the required data from the main memory and potentially P S RN R T e me__—;dle e — ? ' ‘ fl - \i l . D il D must fetch the required data from the main memory and potentially update the cache. update the cache. b. size them larger to increase 12C bus bandwidth. . . T . 5. Use the Byte Offset: The final 4 bits of the address Specify the exact byte within the cache line. In c. size them smaller to ensure a logic zero can be transmitted 5. Use the Byte Offset: The final 2 bits of the ad(%ress specify the exact byte within the cache line. In our example, the byte offset would be the last 4 bits, 0101. our example, the byte offset would be the last 2 bits, 0101. d. size them smaller to decrease overall power consumption during bus operation. This process ensures efficient cache operations and quick data access, utilizing the tag bits to check if the R e S S y 0 ":CL This process ensures efficient cache operations and quick data access, utilizing the tag bits to check if the address is in the cache, the set index to know where to look, and the byte offset to identify the exact byte e. None of the other answers are correct P rI led <z address is in the cache, the set index to know where to look, and the byte offset to identify the exact byte within a cache line. oS : within a cache line. Calculate the number of storage bits the cache will require to hold the s E%fiy(’ffwei,mmfli Qhe@ 35 Pe&mf‘xe esg Direct Set-associative pull low A2 right answer ‘fl ¢ SUA N 14-20MB ) ,_ ,_ , $8 uN he link register (LR) in the Cortex M4 stores the return address when a subroutine Is called. This avoids using the stack and the overhead Ie.‘.erw;j, associated with stack manipulations. Is there every a case where the LR must be stored on the stack? FXDIA -~ P. ‘.“éqé g b‘\lgs 1 LL\[l‘ 1 J‘ s Ul'l 1 £ 1 1 ' ,l : 1 ,.r.-\ Yes if nested, or nested subroutine e 1. T PIT in 4} 1o f ller tl g 1 Hit address bus. Tl S : ‘ 1 14 . \ J g gt LN, (1) [1 point] Expressed in MB: ega bzte s), i e 1 icroy d dress? Write your calculations/answer in the box below. | ,f = ')wiuu', 2 MB Ine Memory Organization Memory Organlzatl e e 0 ..................... DA DA I L g \w “k?'a © msa 4 so P < BB NNEEN Y Qo= SO | . [2 points] Suppose the maxim ilabl f tl lloeid) A * The/steps of a read cycle of SRAM: ress l:vgnerrr!‘i% RIAM Timing, S’teps ofa read cycle of DRAM g tags in your cache is onln this case, there is not enough storage space for all the tag bits. sTop ' b . i YAl aan an bus\ i = e . . : But, you are smart, so you decide to use a set-associative cache ma h me. What is the ACK P o W “ 1 ® g '—y-—fl fz bit dindex bi der to full th soa MM SDA . > Ensure that the chip is activated by making CS low. 5::O_ E awn X to use in order to fully use the av. ive Moo g s W sa .- @ o > - . " 2) The Row Address Strobe (RAS) signal is then activated. 4 ctlvate t UE ln This ensures that data is rea o r&e—mBL \\_e__/fl Data out 3) The Row Address Decoder selects the proper row. g Figure 4: 12C basic wavefgrp. portions > The required data then appears on the data bus. 4) INext tl:’e fiolun:’n addrfis is p(ljalget? o?‘ tgne same address = § -2 048 ~_ ‘A& - (> L\G w Tou is the re ti om the instant Q‘ inesand allowed to stabilize and be latche T 2 1, S é ‘ S ! Y) [5 points] The figure below shows ah bus trarffsmission. Fill in the required information. Hint: the address is pl n the address bus to the point 5) The Column Address Strobe (CAS) signal is then activated. Serae and Rcfresn ) ¢ T ta‘i T Id fievhe Floclyi Ishte:efl::arqu:;d data ' ar\lra|:‘able or:\etheldar:‘aurt:lustlT,c 6) The CAS pin also serves as the Output Enable; so, once the me batween two read cycl ‘ m , b‘) CAS mfinal has stabilized, the sensetamgstplgce 0 N 7) With this i ilabl ?\,s( Output duiiers or the cip, d’ bus. Y rfl‘i\ 8) Bef A 1 rurl h » Place the data to be written on the data bus. e Do * Note that this is a conventional asynchronous read, because the tlmlng signals are not tied to a common (O NACK (b) Choose one answer: (d) The number of data bits trangmitted was: 9 p m » Activate the WR liffe. Only then the data is valid,)- Eycle of SRAM i - [ O Ack O NACK * Tl eps of a write cycle of SRAM: - Iy 4’?1/,)5 » Place the address to be written to on the address bus. aa » Ensure that t ip-i ivated by making CS low. CAS and L/ oy -, acoess time fom RAS 3 = read cycletime Pn,(,lnrw access $me from CAS g, = RAS precharge time I'me