exam2_212_fall_10_25_2019_sol (1)

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ECE 212

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Apr 3, 2024

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Name: ________________________________________ ECE 212 Exam #2 w/ Solutions October 29, 2019 Cover Sheet  This exam is Closed Note, Closed Book, Closed Calculator, No Electronics, No Earbuds.  No correspondence is allowed with anyone other than the instructor/proctor.  Absolutely NO IMs, E-Mails, Verbal Messages, or other communications during the exam!  No Cell Phones, e-watches, or other communications devices, may be used.  It is OK to work on separate paper, but please write answer back into space on test pages . Attach the extra sheets to your exam.  All work must be completed in PENCIL . No ink pen allowed!  This is a 75 minute exam. Please check through the entire test to get the most points, the easiest problems may not be only at the beginning of the test.  Students who arrive late will NOT be given extra time on the exam.  You WILL be required to show your work for full credit!  Partial Credit will be Generous!  Failure to abide by these rules and the NCSU Honor Policy will result in a zero on the exam and will be treated as a violation of the NCSU Code of Student Conduct.  Read and sign the following statement. Failure to sign the statement will result in a zero on the exam. I have neither given nor received unauthorized assistance on this test. I have notified the proctor of any violations of the above policies. Signature: __________________________________________________

Name: __________________________ Question Topic Points Score 1 Circuit Design 1 20 2 State Machines 30 3 PLA 18 4 Circuit Design 2 10 5 Timing 10 6 Random Questions 12 TOTAL 100 Except for name, DO NOT WRITE ON THIS PAGE. Grader : _____________________________________________ ECE 212 Fall 2019 Exam #2 w/ Solutions Page 2 of 11

Name: __________________________ [1] [20 pts] Circuit Design 1 Using the 8:1 Mux shown here, design the circuit to meet the switching equation F F = Ʃ(0,3,5,8,9,11,12,14,15) Choose A,B,C to be select lines to a mux. A = S2, B = S1, C = S0 I0 = D’ I1 = D I2 = D I3 = 0 I4 = 1 I5 = D I6 = D’ I7 = 1 ECE 212 Fall 2019 Exam #2 w/ Solutions Page 3 of 11

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Name: __________________________ [2] [30 pts total] State Machines [a] [2 pts] What type of State Machine is represented by this state diagram? Mealy [b] [1 pts] How many memory elements are required to implement this circuit? 2 [c] [4 pts] Complete the Symbolic Next State and Output Table for this diagram [d] [4 pts] Convert the symbolic table to the encoded state table. ECE 212 Fall 2019 Exam #2 w/ Solutions Page 4 of 11

Name: __________________________ [e] [8 pts] Draw the next state table to complete this circuit with J/K Flip-flops. [f] [11 pts] Draw the complete circuit diagram to implement this design in hardware. ECE 212 Fall 2019 Exam #2 w/ Solutions Page 5 of 11

Name: __________________________ [3] [18 pts] Programmable Logic Arrays (PLAs) Implement the following switching functions on the PLA shown below by marking “x” where a connection should be made. Be sure to label the minterms so that partial credit may be given if needed. F1 = B·E + A·C·E + A’·B’·E’ F2 = A’·D·F + B·D F3 = A’·D·F + B·E’ + A·D·E’ F4 =A·D·E’ + B·E F5 = A’·C·F’ + A·C·E + A’·B’·E’ ECE 212 Fall 2019 Exam #2 w/ Solutions Page 6 of 11

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Name: __________________________ F6 = B·E + A·C·E + B·D [4] [10 pts] Circuit Design Part 2 Implement the following function in a POS design using the 74138 3:8 decoder shown here. F = π(1,3,4,6) ECE 212 Fall 2019 Exam #2 w/ Solutions Page 7 of 11

Name: __________________________ ECE 212 Fall 2019 Exam #2 w/ Solutions Page 8 of 11

Name: __________________________ [5] [10 points] Timing For the D Flip-flop shown here, complete the “Q” row for the timing diagram ECE 212 Fall 2019 Exam #2 w/ Solutions Page 9 of 11

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Name: __________________________ [6] [12 points total] Random Questions [a] [4 pts] Adders Explain the difference between a Half and Full Adder. Draw the symbols if this helps you describe them. A Half-adder has inputs A, B, and outputs Sum, Carry-out. NO Carry-in! A Full-adder has inputs A, B, carry-in, and outputs Sum and Carry-out. [b] [2 pts] What does the “T” in the T Flip-flop mean? Toggle [c] [2 pts] What was the primary use of T flip-flops in older days of design with more discrete components? Divide by 2 on a clock generation to correct the duty cycle to a near-perfect 50%. [d] [2 pts] How many parity bits would be required for a 64-bit word memory architecture? 8 bits to 1 parity. 8 x 1 = 8 parity bits [e] [2 pt] How many ECC bits would be required for a 64-bit word memory architecture? 8 bits to 2 ECC. 8 x 2 = 16 ECC bits ECE 212 Fall 2019 Exam #2 w/ Solutions Page 10 of 11