exam2_212_Fall_2017_sol

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ECE 212

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Name: ________________________________________ ECE 212 Exam #2 w/ Solutions November 2, 2017 Cover Sheet  This exam is Closed Note, Closed Book, Closed Calculator, No Electronics, No Earbuds.  No correspondence is allowed with anyone other than the instructor/proctor.  Absolutely NO IMs, E-Mails, Verbal Messages, or other communications during the exam!  No Cell Phones, e-watches, pagers, or other communications devices, may be used.  It is OK to work on separate paper, but please write answer back into space on test pages . Attach the extra sheets to your exam.  All work must be completed in PENCIL . No ink pen allowed!  This is a 75 minute exam. Please check through the entire test to get the most points, the easiest problems may not be only at the beginning of the test.  Students who arrive late will NOT be given extra time on the exam.  You WILL be required to show your work for full credit!  Partial Credit will be Generous!  Failure to abide by these rules and the NCSU Honor Policy will result in a zero on the exam and will be treated as a violation of the NCSU Code of Student Conduct.  Read and sign the following statement. Failure to sign the statement will result in a zero on the exam. I have neither given nor received unauthorized assistance on this test. I have notified the proctor of any violations of the above policies. Signature: __________________________________________________

Name: __________________________ Question Topic Points Score 1 Moore and Mealy 4 2 Adders 4 3 PLAs 18 4 Circuit Design 20 5 Asynchronous Circuits 24 6 Synchronous Circuits 30 TOTAL 100 Except for name, DO NOT WRITE ON THIS PAGE. Grader : _____________________________________________ ECE 212 Fall 2017 Exam #2 w/ Solutions Page 2 of 10

Name: __________________________ [1] [4 pts total] Moore and Mealy Label each Truth Table below as a Moore or Mealy circuit. George Mealy Edward Moore [2] [4 pts] Adders Explain the difference between a Half and Full Adder. A Half-adder has inputs A, B, and outputs Sum, Carry-out. NO Carry-in! A Full-adder has inputs A, B, carry-in, and outputs Sum and Carry-out. [3] [18 pts] PLAs For the following set of equations, mark the inputs, outputs, and connections required to implement these functions in the given 6x8 PLA. F1 = A·B’·D’ + A·C’·E + A·B·D·E’ F2 = C·D + A’·C·D’ F3 = B·E’ + A’·B’·D’ + A·B·D·E’ F4 = B·E’ + A·B·D·E’ F5 = A·B’·D’ + C·D + A’·B’·D’ ECE 212 Fall 2017 Exam #2 w/ Solutions Page 3 of 10

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Name: __________________________ ECE 212 Fall 2017 Exam #2 w/ Solutions Page 4 of 10

Name: __________________________ [4] [20 points] Circuit Design The switching expression for a combinational circuit is given f(a,b,c,d)=∑ a,b,c,d (1,3,5,9,12,13). [a] [4 pts] Complete the truth table below for this function. [b] [16 pts] Use 3:8 Decoders to implement this function. Assume that the decoders have positive logic for all input and outputs. Show work! ECE 212 Fall 2017 Exam #2 w/ Solutions Page 5 of 10

Name: __________________________ [5] [24 points] Asynchronous State Machines ECE 212 Fall 2017 Exam #2 w/ Solutions Page 6 of 10

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Name: __________________________ [a] [4 pts] Identify the stable states with a circle. Identified on table above. [b] [2 pts] How many storage elements (delays) are required to implement this design? 3. There are 6 states, so next-highest-power of 2 is 8, 2 3 = 8. [b] [15 pts] Trace the following sequence through the table. List the state for each step in the sequence and the resulting output. Traces Shown Above [c] [3 pts] Choose the state bits to prevent any race conditions. States shown above in table. There are several assignment possible combinations which will work. [6] [30 pts] Synchronous Circuit Design You are given the state diagram for a synchronous FSM below. ECE 212 Fall 2017 Exam #2 w/ Solutions Page 7 of 10

Name: __________________________ [a] [6 pts] Use the encoding A=00, B=01, C=11, D=10 to develop the encoded state table. [b] [10 pts] For the JK Flip-flop shown here, convert the next state values to the proper inputs for this flip-flop. ECE 212 Fall 2017 Exam #2 w/ Solutions Page 8 of 10

Name: __________________________ [c] [14 pts] Determine the switching expressions for the memory elements and output to implement using the JK flip flops. Show all work. Do NOT draw the circuit diagram! ECE 212 Fall 2017 Exam #2 w/ Solutions Page 9 of 10

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