WA Unit 2 (Comms & Networking)

Write the specifications and market names of the cables NYA (NV), NYMHY (HO5VV-F), NYM (NVV) and NYY (YVV)

2-T Plip.flop to D Plip.Plop ConverSion.

How do I get the eight BIT Adder Subtracter Module (the square one) on Quartus 2?

What is thte type of signal used in television? a. R3E b. B8E c. F3E c. C3F

For the signal flow graph of the given figure consider the following statements: 1. It has three forward paths. 2. It has three individual loops. 3.lt has two non touching loops. out of above the correct statements are X2 X3 X4 O 1, 2, 3 О 1,3 О 2,3 О 1,2

INTRODUCTION A digital multiplexer or data selector is a logic circuit that accepts several digital data inputs and selects one of them at any given time to pass on to the output. Primarily they are used for data routing which selects a transmission path for outgoing data according to the coding criteria established by binary inputs. The routing of the desired data input to the output is controlled by SELECT inputs (often referred to as ADDRESS inputs). Figure 4.1 shows the functional diagram of a general digital multiplexer. The inputs and output are drawn as wide arrows rather than lines; this indicates that they may actually be more than one signal line. Ior I₁ Data Inputs IN-1 Data Input SELECT inputs Figure 4.1: Functional diagram of digital multiplexer (MUX) A demultiplexer performs the reverse operations. It takes a single input and distributes it over several outputs based on the selector. Figure 4.2 shows the functional diagram for digital demultiplexer (DEMUX). The large…

What is serial in and parallel out?

The principle operation of LVDT is based on the variation of Select one a. Self inductance b. Reluctance c. Mutual inductance d. Permanence

We want to design a digital circuit that converts Gray code (ABC) to Binary code (xyz). Set up a 8-to- 1 line multiplexer so that the output gives y as a function of ABC. "A" is given to the most significant bit of the control inputs of the multiplexer. "C" is given to the least significant bit of the control inputs of the multiplexer.

Suppose you wish to increase the maximum clock frequency of the following circuit (without introducing timing violations or modifying the functional behavior of the circuit aside from introducing delay) through pipelining. Some potential locations for pipelining to be added to wires (labelled with numbers 1-10) are shown below: 1 D Q A DQ D Q 10 B D Q DQ C CLK Select all of the wires to which you would add pipeline registers. (Note, it is OK to increase the latency of the circuit, but not the functionality: for any sequence of input combinations, it should produce the same output combinations) If it is not possible, do not select any wires. 01 2 3 4 5 6 7 8 9 10 U 0 2 H

Create a sequence detector that detects the sequence 1001 or 0110 by using Verilog Code. Construct the modules for both the Moore and Mealy models. Demonstrate your simulation results using the following input sequence for the test fixture (test bench): x= 0010011010010110010110110100

Determine the logic expression for the output Y as a function of the inputs

Write a PIC16F877A program that flash ON the 8-LED's connected to port-B by using two switches connected to port-D (Do & D₁) as shown in figure below, according to the following scenarios: (Hint: Use 500ms delay for each case with 4MHz frequency) 1. When Do=1 then B₁,B3,B7 are ON. 2. When Do 0 then Bo,B2, B4, B5, B6 are ON. 3. When D=1 then B4, B5, B6, B7 are ON. 4. When D₁=0 then B0,B1,B2,B3 are ON. U1 OSC1/CLION 33 OSC2/CLKOUT T 34 5 U2 20 10 35 3 18 10 - 30 -ou-un RB2 2 RA1/AN1 PA3/AN3VREF+ RA4/TOCKIC1OUT RACIANO 0RB3PGM 37 33 4 17 5 10 RB4 39 RA2/ANZ/VREF-CVREF RB5 15 39 7 14 RB6PGC 40 13 RB7/PGO RAS/AN4/SS/C2OUT + 15 RCOT1OSOTICK 10 RECANARD RE1/AN/R REZ/ANTICS ✓ MCLR/Vpp/THV RC2/CCP1 RC3/SCK/SCL RCA/SOISDA RC5/S00 RCB/TX/CK 10 RC1/T10SUCCP2 17 LED-BARGRAPH-RED RC7/RX/DT ROOPSPO RD1/PSP1 R02/PSP2 RD3/PSP3 ROUPSP4 RD5PSP5 ROOPSPO RO7/PSP7 PIC16F877A +5V R2 100R R1 100R